IDENTIFYING CRITICAL LOADS AND A STUDY OF THEIR ACCESS PATTERNS CS752 PROJECT REPORT ANURAG GUPTA, VISHAL KATHURIA { anurag , vishal }@cs.wisc.edu Computer Sciences Department University of Wisconsin, Madison Madison – 53706, WI December 15, 19982ABSTRACT The contribution of this report is an analysis of the access patterns of the loads that are critical to the performance of an out of order processor (henceforth called the Critical Loads). Our measurements reveal that 30%-40% (an in some cases, upto 98%) of the critical load instructions access the same memory location they accessed the last time they were executed. Moreover, in more than 80% of the cases, the successive occurrences of a critical load instruction in the dynamic instruction stream are atleast 512 instructions apart. On the basis of above analysis, we present a memory management technique to decrease the latency of critical loads and speedup the overall performance of an out of order processor. 1. INTRODUCTION There has been a tremendous improvement in the processor performance over the last couple of decades. Today, most processors are capable of extremely high clock rates with complete out of order execution resulting in high performance. But on the other hand, improvement in the main memory performance has not kept pace with the processor performance. For example, processor performance has been increasing at almost 50% per year whereas memory access times have been improving at only 5-10% per year only [2]. As a result, there is a wide gap between the memory and processor performances. A balance should be maintained between the two, which unfortunately has not happened over the years. As a result, the memory access time due to a cache miss is likely to become a major bottleneck in the future. Looking at the other face of the coin, as mentioned earlier, most modern processors are capable of out of order execution. They can buffer the instructions that are waiting for their operands from memory. So, if an instruction is waiting for its data from the main memory, then the processor can execute other independent instructions and still achieve high performance. So, why bother to speed up the critical instructions? On close examination, we see that although the processor can use dynamic scheduling and buffering to execute other independent instructions, it is not always possible to find independent instructions to execute. This will result in the processor to stall, thereby reducing performance. Secondly, although the processor may employ sophisticated branch prediction mechanisms and allows speculative execution to execute instructions out of order, it must always commit the instructions in order. Thus, the finite resources of the processors may also cause it to stall. For example, the reorder buffer and the load/store queues have a finite size, if they are filled up waiting for an instruction at the head of the list, then the processor must stall. Thirdly, although most processors employ sophisticated branch prediction schemes, it mispredicts many times too. If a critical load is feeding a3mispredicted branch, then it will cause the processor to go down the wrong execution path. This will have an effect that although the processor is kept busy, no useful work is done. Thus, it becomes important to identify such critical loads and provide mechanisms to speed up their execution so that they don’t have to wait too long for their operands from memory, thereby allowing instructions that depend on them for their operands not to stall and improve processor performance. We present a study of the access patterns of these critical loads (including a study of their spatial and temporal locality). We also present a hardware scheme that could be employed to decrease the latency of these critical loads. The study of the access patterns of these Critical Loads presents some interesting results, which we discuss and utilize to propose the hardware schemes. The report is organized as follows. In Section 2, we will discuss what we mean by Critical Loads and how we can categorize loads as critical. In Section 3, we discuss the mechanism we have employed to identify these critical loads. Section 4 discusses the implementation details. Section 5 illustrates the results and observations. We interpret the results obtained and make some observations about the spatial and temporal locality of the critical loads. In Section 6 we propose a hardware scheme based on the study of the access patterns of these critical loads. In Section 7 we summarize our work done and point out some of the limitations of our study and in Section 8, we conclude with a mention of some of the future directions. 2. BACKGROUND In the execution stream of instructions, there are certain instructions on which other instructions are dependent for their data values. The data values from memory for these instructions should be fetched as quickly as possible so that the instruction does not have to wait too long. These instructions are Critical and the processor has a Low Latency Tolerance for them. We categorize loads as Critical which fall in the following two categories [1]: 1. The loads on which the branches, especially the ones which are mispredicted depend, and 2. The loads on which a large number of succeeding instructions depend. Thus, all loads in an execution stream of a program can be categorized into the above two categories. If a branch depends on the operand from the load instruction then it must be computed as soon as possible. Also, if there are a large number of instructions that directly or indirectly depend on this load, then this load becomes4critical and needs to be completed quickly otherwise the processor might not be able to tolerate its latency and stall. Hence, these loads becomes critical to the processor performance and it becomes very important to identify these loads and service them as fast as possible. In the next section we describe the scheme that we use to identify the critical loads. 3. IDENTIFICATION OF THE CRITICAL LOADS For identifying the critical loads, we employ the following scheme, which we call the Critical Load Identification Scheme (CLIS): We maintain an instruction window of the last N executed instructions. Instructions enter the window from one end and leave at the other end. Each entry in the Instruction Window contains the instruction and a pointer to a