ChapterSequentialCircuits11Circuits•Combinational circuit‣The output depends only on the input•Sequential circuit‣Has a state‣The output depends not only on the input but also on the state the circuit is inSequential circuit•Constructed from standard gates, but with one or more feedback connections•An unstable state is one that will change a few gate delays later because of the feedback connection•A stable state is one that will persist indefinitely until the input changesAn unstable circuit. A stable circuit.a b dca b c( )a( )bFigure 11.1SR Latch•The SR latch has two stable states•When SR = 00, output Q can be 0 or 1 depending on the state of the latch•S = 1 sets ouput Q to 1•R = 1 resets output Q to 0QQRSFigure 11.2TimeInitial0Tg2TgStabilityStableUnstableUnstableStableR0000S0111Q0001—Q1100Figure 11.3TimeInitial0StabilityStableStableS10R00Q11—Q00Figure 11.4Figure 11.5 SRQQa b c d e–System clock•Controls the state transitions of all the sequential circuits to happen at the same time•Sequence of regularly spaced pulses with period TCkTFigure 11.6Clocked SR flip-flop•Two AND gates that act as an enable•Only when Ck is high can the S and R inputs affect the state of the flip-flop•The effect is to digitize the time axisBlock diagram.( )a Implementation.QQ( )bSRCkSCkRQQFigure 11.7Figure 11.8SRCkQa b c d eThe feedback problem•Flip-flops are often used in circuits with feedback connections (in addition to the internal feedback in the latch)•Therefore, unstable states are possible•There are two design solutions to the feedback problem‣Edge-triggered flip-flops‣Master-slave flip-flopsInputCombinationalcircuitOutputSCkRQQFigure 11.9Master-slave SR flip-flop•Solves the instability problem caused by possible external feedback•Input goes to the master latch first, and then from the master to the slave, in four steps•The threshold of a gate is the value of the input signal that causes the output to change•Engineers can make gates with thresholds a little above or a little below the average value between 0 and 1(a) Block diagram. (b) Implementation.SRQQS2R2Q2Q2Threshold V1Threshold V2Threshold V2Master SlaveSCkRQQCkFigure 11.10 (a) Block diagram. (b) Implementation.SRQQS2R2Q2Q2Threshold V1Threshold V2Threshold V2Master SlaveSCkRQQCkTiming detail of a single Ck pulse•t1: Isolate slave from master•t2: Connect master to input•t3: Isolate master from input•t4: Connect slave to mastert1t2t3t4V1V2Clock signalTimeFigure 11.11Effect on timing•The output changes on the falling edge of the Ck pulse and depends on the external SR input at that timeSRCkQ Figure 11.12Characteristic table•A truth table is not adequate to describe a flip-flop, because its output depends on more than its input•Given the inputs at time t and the state at time t, the characteristic table shows the state at time t + 1, that is, after one clock pulseConditionNo changeResetSetNot definedS(t)00001111R(t)00110011Q(t)01010101Q( t + 1)010011––Figure 11.1301010010000101Figure 11.14Four common flip-flops•SR! Set/reset•JK! Set/reset/toggle•D! Data or delay•T! ToggleExcitation table•The excitation table is a design tool for constructing circuits from a given type of flip-flop•Given the desired transition from Q(t) to Q(t +1), what inputs are necessary to make the transition happen?Q(t)0011Q(t + 1)0101R(t)s010010sS(t)Figure 11.15JK flip-flop•Resolves the undefined transition in the SR flip-flop•When JK = 00, output Q can be 0 or 1 depending on the state of the latch•J = 1 sets ouput Q to 1 (like S)•K = 1 resets output Q to 0 (like R)•JK = 11 toggles from one state to the other(b) Characteristic table.K(t)Q(t + 1)J(t)No changeResetSetToggle01001110010101010011001100001111Q(t) Condition(a) Block diagram.JCkKQQFigure 11.16JK flip-flop design•Must design a three-input two-output combinational circuit•Inputs‣J(t), K(t), Q(t)•Outputs‣S(t), R(t)InputCombinationalcircuitOutputSCkRQQFigure 11.9Design table•Step 1: Given Q(t), J(t), and K(t), list the desired state after the transition Q(t + 1)•Step 2: Given Q(t) and Q(t + 1), use the excitation table to list the required input for S(t) and R(t)•Step 3: Use Karnaugh maps to design minimized two-level combinational circuits for S(t) and R(t)S(t) R(t)0011!!00!00!Q(t + 1)001110010110J(t) K(t)001101100011Q(t)000011110110Figure 11.17(a) Karnaugh map for S. (b) Karnaugh map for R.JKQ01Q01×1 1×00 01 11 10JK00 01 11 101 1× ×Figure 11.18QQKJCkSCkRQQFigure 11.19D flip-flop•The “delay” or “data” flip-flop•Only one input, D•Regardless of the current state Q(t), the state after the clock pulse Q(t + 1) will be the same as D(t)Figure 11.20562 Chapter 11 Sequential CircuitsFigure 11.20The D flip-flop.QQDCk(a) Block diagram. (b) Characteristic table.(c) A timing diagram.D(t) Q(t)00110101 Q(t + 1)0011ConditionDelayDelayDCkQThe D Flip-FlopThe D flip-flop is a data flip-flop with only one input, D, besides the clock. Figure11.20(a) is its block diagram and (b) is its characteristic table. The table shows thatQ(t + 1) is independent of Q(t). It depends only on the value of D at time t. The Dflip-flop stores the data until the next clock pulse. Part (c) of the figure shows a tim-ing diagram. This flip-flop is also called a delay flip-flop because on the timing dia-gram, the shape of Q is identical to that of D except for a time delay.Figure 11.19Implementation of the JK flip-flop.QQKJCkSCkRQQ71447_CH11_Chapter11.qxd 1/28/09 1:26 AM Page 562(b) Karnaugh map for S.(a) Design table.DQ0101×1(c) Karnaugh map for R.DQ01×101S(t) R(t)01×0×001Q(t + 1)0110Q(t) D(t)00110110Figure 11.21(b) Karnaugh map for S.(a) Design table.DQ0101×1(c) Karnaugh map for R.DQ01×101S(t) R(t)01×0×001Q(t + 1)0110Q(t) D(t)00110110QQDCkSCkRQQFigure 11.22T flip-flop•The “toggle” flip-flop•Only one input, T•If T = 0, the state remains unchanged•If T = 1, the state toggles from 0 to 1 or from 1 to 0QQCkT(a) Block diagram.Figure 11.23(b) Characteristic table.T(t)Q(t + 1)No changeToggle011001010011Q(t) ConditionFlip-flop design•Any given flip-flop can be constructed from any other flip-flop with the right combinational circuit•Use the excitation table for the flip-flop from which you are constructing the given flip-flop(a) The JK flip-flop.Q(t)0011Q(t + 1)010101ssJ(t) K(t)ss10(b) The D flip-flop.Q(t + 1)0101(c) The T flip-flop.Q(t +