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SJSU EE 270 - Review of Switching Algebra

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Lecture01.pdfLecture1A.pdfReview of switching algebra.pdfReview of switching algebraBOOLEAN ALGEBRAFundamentals of BooleanLaws of BooleanContd..Boolean Functions & Logical OperationsBoolean Functions & Logical OperationsMINTERMS, MAXTERMS OF 3 VARIABLESMinterm TheoremsMaxterm TheoremsAsynch vs Synch design.pdfSynchronous vs AsynchronousSynchronous AdvantagesSynchronous disadvantagesAsynchronous advantagesAsynchronous ChallengesControl CircuitsDelays and hazardsDelays, Hazards & Arbitration (cont.)Prior WorksTopics of Interest in ACDLecture1B.pdflecture1slides.pdfCH2_Slides.pdfDefinitionsFig 2-1 Gate NetworkFrom Page 45-46Fig 2-2 VHDL Program StructureFig 2-3 & Fig 2-4(i) 4-bit Binary AdderFig 2-3 & Fig 2-4(ii)From Page 49VHDL ProcessesFig 2-5 D Flip-flop ModelFig 2-7 J-K Flip-flop ModelFig 2-8 Equivalent Representations of a Flowchart Using Nested Ifs and ElsifsFig 2-9 4-to-1 MultiplexerMultiplexer Example from Pg. 55Fig 2-10 Compilation, Elaboration, and SImulation of VHDL CodeFig 2-11 VHDL Code for Simulation ExampleFig 2-12 Signal Drivers for Simulation ExampleFig 2-13(a) Behavioral Model for Figure 1-17Fig 2-13(b)Fig 2-14 Waveforms for Figure 2-13Fig 2-15 Sequential Machine Model Using EquationsFig 2-16 Structural Model of Sequential MachineFig 2-17 Waveforms for Fig 2-16Fig 2-18(a) Behavioral Model for Fig 1-17 Using a Single ProcessFig 2-18(b)Fig 2-19 Process Using VariablesFig 2-20 Process Using SignalsFrom Pg. 67From Pg. 68From Pp. 69-70Fig 2-21 Sequential Machine Model Using State TableVHDL OperatorsExamples of VHDL OperatorsExamples of Shift OperatorsVHDL FunctionsFrom Pg. 72Fig 2-22 Add FunctionFig 2-23 Procedure for Adding Bit_vectorsTable 2-1 Parameters for Subprogram CallsFrom Pg. 76Appendix B Bit Package(i)Appendix B Bit Package(ii)Appendix B Bit Package (iii)Appendix B Bit Package (iv)Fig 2-24 Two 74163 Counters Cascaded to Form an 8-bit CounterFig 2-25 74163 Counter ModelFig 2-26 VHDL for 8-bit CounterReview of switching algebraBoolean AlgebraFundamental TheoremsLaws of Boolean AlgebraBoolean Functions & Logical OperationsBOOLEAN ALGEBRA• A Boolean algebra is a closed algebraic system, containing a set K of two or more elements and the two operators ‘.’ and ‘+’; alternatively, for every a and b in set K, a.b belongs to set K and a+b belongs to set K ( + is called OR and . is called AND) and where ‘=‘ represents the equivalence relation and ‘ is the complement.• Boolean algebraic system obeys the following fundamentals of boolean.Fundamentals of Boolean1. Associativity: a+(b+c) = (a+b)+c, a.(b.c) = (a.b).c2. Commutativity:a+b = b+a, a.b = b.a3.Distributivity:a+b.c = (a+b).(a+c), a.(b+c) = (a.b)+(a.c)4.Identity Element:a+0=a, a.1= a5.Complement:Each member of B has a complement within B such as a+a’ = 1a.a’ = 0Laws of BooleanTheorem 1: Idempotency(a) a+a=a, (b) a.a=aTheorem 2: Null elements for + and . Operators(a) a+1=1(b) a.0=0Theorem 3: Involution(a’)’ = aTheorem 4: Absorption(a) a+ab = a(b) a(a+b) = aTheorem 5:(a) a+a’b = a+b(b) a(a’+b) =ab…ContdContd..Theorem 6:(a) ab+ab’ = a(b) (a+b)(a+b’) = aTheorem 7:(a) ab+ab’c =ab +ac(b) (a+b)(a+b’+c) = (a+b)(a+c)Theorem 8: DeMorgan’s theorem(a) (a+b)’ = a’.b’(b) (a.b)’ = a’+b’Theorem 9: Consensus(a) ab+a’c+bc = ab+a’c(b) (a+b)(a’+c)(b+c) = (a+b)(a’+c)Boolean Functions & Logical Operations• The normal form– Literal– Product & Sum terms– SOP & POS• Canonical forms– Disjunctive Canonical Form (DCF)– Conjunctive Canonical Form (CCF)Boolean Functions & Logical Operations• Minterms: A product of ‘n’ variables, where each of the ‘n’ variables appears exactly one time in complemented or uncomplemented form is called the minterm of the ‘n’ variables Ex. A’BC, XY’Z, a’b’c’ are minterms of 3 variables• Maxterms: A sum of ‘n’ variables, where each of the ‘n’ variables appears exactly one time in complemented or uncomplemented form is called the maxterm of the ‘n’ variablesEx. A+B+C+D’,W+ X’+Y+Z, a+b+c’+d’ are maxterms of 4 variables• Form conversions∑mi = ∏Mj, i and j are two partitions of the entire set of 2nsubsets of either minterms (m’s) or maxterms (M’s)MINTERMS, MAXTERMS OF 3 VARIABLESBinary Minterm notationMinterms Maxterms Maxterm notation000 m0A’B’C’ A+B+C M0001 m1A’B’C A+B+C’ M1010 m2A’BC’ A+B’+C M2011 m3A’BC A+B’+C’ M3100 m4AB’C’ A’+B+C M4101 m5AB’C A’+B+C’ M5110 m6ABC’ A’+B’+C M6111 m7ABC A’+B’+C’ M7Minterm TheoremsinDijijjiijijiiiMmdffmfandmffandfs: partitiontermscjiwhenmmbmann−−−===⇒==⇒≠==∑∑∑12'120.2min2.0.1.Maxterm TheoremsinnnmMdffMjfandMiffandfs: partitiontermscjiwhenMMbMaDijijijijiii−−==⇒==⇒≠==∏∏∏+−=12.2max2.1.0.'120Synchronous vs Asynchronous• Synchronous systems– All events are synchronized to a single clock• Asynchronous systems– Synchronization is achieved without a clock• The world that we live in is an asynchronoussystem or a synchronous system?Synchronous Advantages• Simple way to implement sequencing• Widely taught and readily understood• Available components• Simple way to deal with noise and hazardSynchronous disadvantages• Clock distribution, clock skew• Worst case design• Sensitive to variations in physical parameters• Not modular• High power consumptionAsynchronous advantages• Elimination of clock problem• Average case performance• Adaptive to processing and environmental variations• Component modularity• Lower system power requirementsAsynchronous Challenges• Lack of mature CAD tools• Large area of overhead to remove hazards• Average-case delay can be large• Lack of design experienceControl Circuits• Signaling Protocols– two-cycle (level-signaling)– four-cycle– The C-element– Bundled data & dual rail encoding• Completion signals– Internal clock– Delay element– Special functions– Current sensing completion detectionDelays and hazards• Delay models: pure, inertial, bounded, unbounded• Input/output mode & environmental timing constraint• Classes of AC– Delay-insensitive– Quasi-delay-insensitive– Speed independent– Self-time circuitDelays, Hazards & Arbitration (cont.)• Hazards: SIC Hazards & MIC Hazards• Hazards free minimization• Arbitration– Mutual Exclusion Element– Tree-structured N-way arbiter (using C-element)– Various other arbiter design for high-performancePrior Works• Huffman Circuit•


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