CSCE 3953 System Synthesis and Modeling Lecture 6 Synthesis with Synopsys Design CompilerOutlineSynthesisLogic SynthesisWhy Synthesis?Logic SynthesisFunctional DescriptionTranslationMapping/OptimizationOptimization: Constraint-DrivenStatic Timing AnalysisOptimization: Slack-DrivenSynthesis/Physical SynthesisOutlineRunning DCDC Setup FilesDC Setup Files - exampleLibrary SetupLibrary Setup - continuedLibrary Setup - continuedLibrary Setup - continuedOutlineAnalyzeElaborateread_fileOutlineOptimization: Constraint-DrivenDesign Constraint TypesOptimization PriorityConstraint GuidelinesConstraint ValidationDesign Rule Constraints (DRC)Optimization Constraints: Operating ConditionsOptimization Constraints: Net ParasiticsOptimization Constraints: Input/OutputExampleOptimization Constraints: ClocksOptimization Constraints: ClocksOptimization Constraints: ClocksOptimization Constraints: ClocksExampleOptimization Constraints: DeratingOptimization Constraints: PowerOptimization Constraints: AreaOptimization Constraints: StructuralOptimization Constraints: FunctionalOptimization Constraints: FunctionalOptimization Constraints: AlgorithmicOptimization Constraints: AlgorithmicExampleOutlineDefinitionsTop-Down CompileBottom-Up CompileGuidelinesMeeting Timing Goalscompile_ultraSetting Critical Range / Group PathUngroup HierarchyRegister RetimingUse Fast DesignWare ComponentsArea ConsiderationClock GatingDesignWare SelectionRuntime MethodologySummaryOutlineAnalysis Flowreport_designreport_clockcheck_designcheck_timingCustomizing Compile Logreport_qorreport_constraintreport_constraint –allreport_timingreport_delay_calculationAdditional CommandsAnalysis SummaryTake a Break!CSCE 3953 System Synthesis and Modeling Lecture 6 Synthesis with Synopsys Design CompilerInstructor: Dr. Jia DiSome slides are borrowed from Synopsys Galaxy 2006 Seminar Series2Outline Synthesis Overview Design Compiler Flow Design Compiler Setup Reading the design Design Constraints Compile Strategies Design Analysis3SynthesisCombining pre-existing elements to form something new4TPLogic SynthesisCombining primitive logic functions to form a design netlist that meets functional and design goalsTPTPTPNetlistFunctional Description (HDL)GoalsTP=Technology Primitive5Why Synthesis?LayoutGate1Mresidue = 16’h0000;if (high_bits == 2’b10)residue = state_table[index];elsestate_table[index] = 16’h0000;HDL10kABCDZTransistor5MPolygon100M# of ElementsComplexityEffortTimeCost6Logic SynthesisTarget Technology(standard cells)Logic Synthesis = Translation + Mapping + OptimizationGeneric Boolean (GTECH)Translation(read)Mapping/Optimization(compile)residue = 16’h0000;if (high_bits == 2’b10)residue = state_table[index];elsestate_table[index] = 16’h0000;Hardware Description Language (HDL)7Functional Description Written in Hardware Description Language (HDL) Verilog/VHDL Register Transfer Level (RTL) Synchronous => reliable behavior Simplifies timing verification Simplifies optimization algorithms Optimal results Coding style affects results8TranslationGeneric Boolean (GTECH)Translation(read)residue = 16’h0000;if (high_bits == 2’b10)residue = state_table[index];elsestate_table[index] = 16’h0000;Hardware Description Language (HDL) Converts HDL to functional boolean equivalent HDL syntax/rule checks Optimizes HDL Arithmetic function mapping Sequential function mapping Combinational function mapping9Mapping/OptimizationGeneric Boolean (GTECH)Mapping/Optimization(compile) Maps Boolean functions to technology specific primitive functions Modifies mapping to meet design goals Design Rules Timing Area PowerTarget Technology(standard cells)10Design goals (constraints) drive optimizationLargeAreaSmallShortDelayLong••••••Optimization: Constraint-Drivencreate_clock –period 10 –name CLK [get_port clock_in]set_input_delay 4 -clock CLK [get_ports data_in*]set_output_delay 3.5 -clock CLK [get_ports data_out*]set_max_area 011D QQBD QQBFF2FF3TOPACLKZ STA breaks designs into sets of signal paths Each path has a startpoint and an endpoint: Startpoints:• Input ports• Clock pins of Flip-Flops or registers Endpoints:• Output ports• All input pins of sequential devices (except clock pins)Static Timing Analysis12FF1/clkFF2/clkFF2/D1.1ns5.1ns1ns5nsSetup11ClkData RequiredF1FF2DData ArrivalF1FF1QCLKCLKU3U2Optimization: Slack-Driven13Synthesis/Physical SynthesisSynthesis(DC, DCT)RTLTiming ConstraintsFloorplanStatic Timing (DC/DCT/PC/PT)Formal Equivalence (FM)Power Analysis (DC/DCT/PC/PT-PX)MeetsSpec?NoDFTYesTiming/Logic LibraryIP Library(DW)Physical LibraryScan-Ready NetlistSynthesisHDL TranslationMappingStatic TimingPlacementRouting EstimationOptimizationDesign Rule FixingDC=Design Compiler DCT=DC Topographical PC=Physical Compiler PT=PrimeTime FM=Formality PT-PX=PrimeTime-PX DW=DesignWareresidue = 16’h0000;if (high_bits == 2’b10)residue = state_table[index];elsestate_table[index] = 16’h0000;Hardware Description Language (HDL)Target Technology(standard cells)14Outline Synthesis Overview Design Compiler Flow Design Compiler Setup Reading the design Design Constraints Compile Strategies Design AnalysisSetupReadConstrainCompileAnalyze15 Invoking DC> dc_shell -tclor> design_vision -tcl setenv PATH $SYNOPSYS/$ARCH/syn/bin/dc_shell• $SYNOPSYS - installation location on your network• $ARCH - linux, sparcOS5, sparc64, etc…Best Practice: Early in the design phase is a good time to decide on design naming conventions, design style guides, common design directory structures, and revision control systems.Running DC16DC Setup Files Setup files automatically read at DC startup .synopsys_dc.setup Possible locations (read in this order)1. Root setup:$SYNOPSYS/admin/setup/.synopsys_dc.setup2. Home setup: $HOME/.synopsys_dc.setup (optional)3. Local setup:./.synopsys_dc.setup (optional) Use to customize the work environment17DC Setup Files - example# TCL-subset .synopsys_dc.setup file must # have the # character on the first line of the fileset search_path ". /synopsys/libraries/syn $search_path"set target_library "lsi_10k.db"set synthetic_library "standard.sldb dw_foundation.sldb"set link_library "* $target_library $synthetic_library"set symbol_library "lsi_10k.sdb"define_design_lib MY_WORK -path ./WORK# example: removing high drive inverterset_dont_use lsi_10k/IVP18Library Setup search_path