CSCE 3953 System Synthesis and Modeling Lecture 6 Synthesis with Synopsys Design Compiler Instructor Dr Jia Di Some slides are borrowed from Synopsys Galaxy 2006 Seminar Series Outline Synthesis Overview Design Compiler Flow Design Compiler Setup Reading the design Design Constraints Compile Strategies Design Analysis 2 Synthesis Combining pre existing elements to form something new 3 Logic Synthesis Combining primitive logic functions to form a design netlist that meets functional and design goals Functional Description HDL Goals TP TP Netlist TP TP TP Technology Primitive 4 Why Synthesis HDL 10k residue 16 h0000 if high bits 2 b10 residue state table index else state table index 16 h0000 Gate 1M Transistor 5M of Elements Complexity A C B D Z Polygon 100M Effort Time Cost Layout 5 Logic Synthesis Logic Synthesis Translation Mapping Optimization residue 16 h0000 if high bits 2 b10 residue state table index Translation read else state table index 16 h0000 Mapping Optimization compile Hardware Description Language HDL Generic Boolean GTECH Target Technology standard cells 6 Functional Description Written in Hardware Description Language HDL Verilog VHDL Register Transfer Level RTL Synchronous reliable behavior Simplifies timing verification Simplifies optimization algorithms Optimal results Coding style affects results 7 Translation residue 16 h0000 if high bits 2 b10 residue state table index else state table index 16 h0000 Hardware Description Language HDL Converts HDL to functional boolean equivalent HDL syntax rule checks Optimizes HDL Arithmetic function mapping Sequential function mapping Combinational function mapping Translation read Generic Boolean GTECH 8 Mapping Optimization Maps Boolean functions to technology specific primitive functions Modifies mapping to meet design goals Generic Boolean GTECH Mapping Optimization compile Design Rules Timing Area Power Target Technology standard cells 9 Optimization Constraint Driven create clock period 10 name CLK get port clock in set input delay 4 clock CLK get ports data in set output delay 3 5 clock CLK get ports data out set max area 0 Large Area Small Short Delay Long Design goals constraints drive optimization 10 Static Timing Analysis TOP A D Q FF2 QB D Q FF3 QB Z CLK STA breaks designs into sets of signal paths Each path has a startpoint and an endpoint Startpoints Input ports Clock pins of Flip Flops or registers Endpoints Output ports All input pins of sequential devices except clock pins 11 Optimization Slack Driven FF1 FF2 Q F1 Clk CLK D U2 U3 F1 CLK FF1 clk 1 1ns Data Arrival Data Required 5 1ns FF2 D Setup FF2 clk 1ns 5ns 11 12 Synthesis Physical Synthesis RTL Timing Constraints Floorplan Timing Logic Library IP Library DW Physical Library Synthesis HDL Translation residue 16 h0000 if high bits 2 b10 residue state table index else state table index 16 h0000 Hardware Description Language HDL Synthesis DC DCT Static Timing DC DCT PC PT Formal Equivalence FM Power Analysis DC DCT PC PT PX Mapping Static Timing No Placement Meets Spec Routing Estimation Optimization Design Rule Fixing Scan Ready Netlist Yes Target Technology standard cells DFT DC Design Compiler DCT DC Topographical PC Physical Compiler PT PrimeTime FM Formality PT PX PrimeTime PX DW DesignWare 13 Outline Synthesis Overview Design Compiler Flow Design Compiler Setup Reading the design Design Constraints Compile Strategies Design Analysis Setup Read Constrain Compile Analyze 14 Running DC Invoking DC dc shell tcl or design vision tcl setenv PATH SYNOPSYS ARCH syn bin dc shell SYNOPSYS installation location on your network ARCH linux sparcOS5 sparc64 etc Best Practice Early in the design phase is a good time to decide on design naming conventions design style guides common design directory structures and revision control systems 15 DC Setup Files Setup files automatically read at DC startup synopsys dc setup Possible locations read in this order 1 Root setup SYNOPSYS admin setup synopsys dc setup 2 Home setup HOME synopsys dc setup optional 3 Local setup synopsys dc setup optional Use to customize the work environment 16 DC Setup Files example TCL subset synopsys dc setup file must have the character on the first line of the file set set set set set search path synopsys libraries syn search path target library lsi 10k db synthetic library standard sldb dw foundation sldb link library target library synthetic library symbol library lsi 10k sdb define design lib MY WORK path WORK example removing high drive inverter set dont use lsi 10k IVP 17 Library Setup search path Allows files to be read in without specifying directory path in the command Directories in which DC will look for library design db files during a link target library Technology cell library files e g lsi 10k db Compile chooses inferred cells from target library 18 Library Setup continued synthetic library Library of DesignWare components dw foundation sldb Advanced set of IP components optional to DC Wide variety moderate high performance arithmetic architectures Fifos stacks counters digital PLL arbiters priority encoders SRAM models ECC CRC debugger decoders encoders more Macrocells 8051 microcontroller 16550 UART Memory BIST controller AMBA peripherals I2C UART SSI APB AHB 19 Library Setup continued link library Used during design linking pre and post compile All cells in a design must be in one of the link libraries Inferred chosen during compile based on RTL functionality Instantiated specific cell instance placed in design RTL link library must always start with indicating loaded designs should be searched first when linking All synthetic and target libraries must be included in link library 20 Library Setup continued define design lib Directory where DC places intermediate design files default is directory in which DC is run set dont use lib cell Specifies cells of a target library or implementations of a synthetic library to not use during compile Best Practice If your technology library has many drive strengths for each cell function consider using set dont use for the highest drive strength of each cell function After routing if you need to up size cells to a higher drive to overcome larger than anticipated capacitances you can remove the set dont use 21 Outline Synthesis Overview Design Compiler Flow Design Compiler Setup Reading the design Design Constraints Compile Strategies Design Analysis Setup Read Constrain Compile Analyze 22 Analyze Translates HDL to intermediate format