Application ReportSPRA487C - September 20011TMS320C6000 McBSP Interface to SPI ROMShaku AnjanaiahVassos SoteriouDigital Signal Processing SolutionsABSTRACTThe TMS320C6000 (C6000) Multichannel Buffered Serial Port (McBSP) is designed tointerface to a device that supports synchronous Serial Peripheral Interface (SPI). Thisdocument describes the hardware interface between the McBSP and a SPI ROM. TheMcBSP operates as the master in a user-specified clock stop (CLKSTP) mode in order tocommunicate with the SPI ROM. The McBSP initialization and control register programmingis also discussed.Contents1 Design Problem 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Solution 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin Configuration 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 McBSP Initialization 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Timing Analysis 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . List of FiguresFigure 1. McBSP Master Interface to SPI Slave Device 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2. Receive Control Register (RCR for SPI Master) 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 3. Transmit Control Register (XCR for SPI Master) 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 4. Sample Rate Generator Register (SRGR for SPI Master) 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 5. Pin Control Register (PCR for SPI Master) 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 6. Serial Port Control Register (SPCR for SPI Master) 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 7. Clock Stop Mode Options 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 8. C6000 Timing, CLKSTP = 11b, CLKXP = 0 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . List of TablesTable 1. McBSP Register Values for 200 MHz CPU Clock 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 2. Timing Numbers for McBSP as SPI Master 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3. Timing Analysis for SPI Master and Slave 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS320C6000 and C6000 are trademarks of Texas Instruments.All trademarks are the property of their respective owners.SPRA487C2TMS320C6000 McBSP Interface to SPI ROM1 Design ProblemHow do I interface the Serial Peripheral Interface (SPI) ROM to the TMS320C6000?1.1 SolutionThe multichannel buffered serial port (McBSP) in the TMS320C6000 interfaces to a SPI ROMwith no glue logic. A SPI system is typically a 4-wire interface comprising serial data in, serialdata out, serial clock, and device select. The McBSP provides this 4-wire interface via DR, DX,CLKX, and FSX pins, respectively.The McBSP supports the SPI interface for a synchronous, full-duplex, variable element length(element length is fixed for a given transfer), master or slave mode back-to-back transmissionand reception. This feature is achieved by using the clock-stop (CLKSTP) mode of the McBSP.This document discusses the McBSP interface to an Atmel SPI serial CMOS EEPROM, whichcan only be a slave. The McBSP as a SPI master, generates the required control signals andclocking to the slave.2 Pin ConfigurationFor the McBSP to master the interface, you must configure CLKX and FSX pins of the serial portas outputs only. CLKX can be generated either via the C6000 CPU clock or via an external clocksource input on the CLKS pin. In SPI mode, a SPI system clock or any other clock source candrive CLKS if present. The clock divide …
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