Digital Design Combinational Logic Blocks Credits Slides adapted from J F Wakerly Digital Design 4 e Prentice Hall 2006 C H Roth Fundamentals of Logic Design 5 e Thomson 2004 A B Marcovitz Intro to Logic and Computer Design McGraw Hill 2008 R H Katz G Borriello Contemporary Logic Design 2 e Prentice Hall 2005 1 Multiplexers Data Selectors A multiplexer MUX for short is a digital switch it passes connects one of its data inputs to the output the data input selected is a function of a set of control inputs called selection inputs A 0 1 Z I0 I1 Two alternative forms for a 2 1 Mux truth table Z A I0 A I1 I1 0 0 0 0 1 1 1 1 I0 0 0 1 1 0 0 1 1 A 0 1 0 1 0 1 0 1 Z 0 0 1 0 0 1 1 1 2 Multiplexers cont d 2n 1 Z mk I k k 0 3 Gate level implementation of muxes 2 1 mux 4 1 mux 4 Cascading multiplexers Large multiplexers can be made by cascading smaller ones I0 I1 I2 I3 I4 I5 I6 I7 4 1 mux alternative implementation 8 1 mux 2 1 mux Z 4 1 mux I0 I1 2 1 mux I2 I3 2 1 mux I4 I5 2 1 mux I6 Control signals B and C simultaneously choose I7 one of I0 I1 I2 I3 and one of I4 I5 I6 I7 2 1 mux B C A Control signal A chooses which of the upper or lower mux s output to gate to Z C 8 1 mux 4 1 mux Z A B 5 Multiplexers as general purpose logic A 2n 1 multiplexer can implement any function of n variables with the variables used as control inputs and the data inputs tied to 0 or 1 Example F A B C m0 m2 m6 m7 A B C A BC ABC ABC A B C 1 A B C 0 A BC 1 A BC 0 AB C 0 AB C 0 ABC 1 ABC 1 Z A B C I0 A B CI1 A BC I2 A BCI3 AB C I4 AB CI5 ABC I6 ABCI7 1 0 1 0 0 0 1 1 0 1 2 3 4 8 1 MUX 5 6 7 S2 S1 S0 A B C 6 Z F Multiplexers as general purpose logic cont d Generalization data inputs can also be tied to variables not just 0 s an 1 s n 1 mux control variables single mux data variable I0 I1 In 1 In F 0 0 0 1 1 1 0 1 0 1 0 In In 1 four possible configurations of truth table rows can be expressed as a function of In 7 Activity Realize F B CD ABC with a 4 1 multiplexer A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Z 0 0 1 0 0 0 0 0 0 0 1 0 1 1 0 0 0 when B C D when B C A when BC 0 when BC 0 D A 0 0 1 4 1 MUX 2 3 S1 S0 B F C Z B C 0 B C D BC A BC 0 8 Multiplexer with bus inputs and outputs 9 Demultiplexers Route a single input to one of many outputs as a function of a set of control inputs x 1 8 demux y0 y1 y2 y3 y4 y5 y6 y7 3 s 2 0 10 Three State Buffers Normally a logic circuit will not operate correctly if the outputs of two or more gates or other logic devices are directly connected to each other multiple drivers conflict B1 B2 1 0 The two driving blocks fight with each other Use of tri state logic permits the outputs of two or more gates or other logic devices to be connected together 11 buffers are a k a drivers Tri state Buffers cont d When the enable B is 1 the output C equals A When the enable B is 0 the output C acts like an open circuit In this case the output C is effectively disconnected from the buffer output so that no current can flow This is often referred as Hi Z high impedance state because the circuit offers a very high impedance to the flow of current 12 Tri state Buffers application examples 13 Tri state Buffers application examples cont d 14 Tri state buffers application examples cont d 15 Tri state Buffers application examples cont d 16 Decoders A decoder is a logic circuit that converts coded inputs into coded outputs Each input code word produces a different output code word there is a one to one mapping between inputs and outputs 17 Decoders cont d Decimal 18 Binary Decoders The most common decoder circuit is an n to 2n decoder or binary decoder 19 Binary Decoders cont d 20 Binary Decoders cont d 21 Gate level implementation of decoders active high enable G 1 2 decoders active low enable O0 S G O0 S O1 G O0 active high enable 2 4 O1 decoders O1 G O0 active low enable O1 O2 O2 O3 O3 22 S1 S0 S1 S0 Decoders as general purpose logic n to 2n decoders can implement any function of n variables with the variables used as control inputs the appropriate minterms summed to form the function 0 1 2 3 3 8 DEC4 5 6 7 S2 S1 S0 A B C A B C A B C A BC A BC AB C AB C ABC ABC decoder generates appropriate minterm based on control signals it decodes control signals 23 Decoders as general purpose logic cont d F1 A BC D A B CD ABCD F2 ABC D ABC F3 A B C D 0 1 2 3 4 5 6 4 16 7 DEC 8 9 10 11 12 13 14 15 A B CD A B C D A B C D A B CD A B CD A BC D A BC D A BCD A BCD AB C D AB C D AB CD AB CD ABC D ABC D ABCD ABCD F1 F2 F3 24 Encoders An encoder performs the inverse function as a decoder The simplest encoder to build is a 2n to n binary encoder 25 Priority Encoders I7 I6 I5 I4 I3 I2 I1 I0 A2 A1 A0 IDLE 0 0 0 0 0 0 0 0 0 0 0 1 1 x x x x x x x 1 1 1 0 0 1 x x x x x x 1 1 0 0 0 0 1 x x x x x 1 0 1 0 0 0 0 1 x x x x …