8-Bit ALUAgendaAbstractIntroductionBlock DiagramFunction TableSummary of ResultsLongest Path CalculationsSchematic - OverallSchematic & Layout – AOI3333Schematic & Layout – Black CellSimulation – NC Verilog - ADDSimulation – NC Verilog - SUBSimulation – NC Verilog - ORSimulation – SPICE – Worst Case (Schematic)Simulation – SPICE – 2-bit Addition (Schematic)Simulation – SPICE – Power Usage (Schematic)Layout - OverallVerification – LVS ReportCost AnalysisLessons LearnedSummaryAcknowledgements18-Bit ALUKin Fu TangRobert LastJoseph RoosmaAdnan AlamAdvisor: David W. ParentMay 8, 20062Agenda•Abstract•Introduction–Purpose–Simple Theory•Summary of Results•Project (Experimental) Details•Results•Cost Analysis•Conclusions3Abstract•An 8-bit ALU using a Han-Carlson carry network was designed. It was shown through simulations to operate at a clock frequency of 200MHz, using 25.28mW of Power and requiring an area of XxX m24Introduction•An ALU is an important building block in digital systems which carries out the basic arithmetic and logic.•Depending on the supplied control signals, the ALU is designed to carry out the following operations on two 8-bit numbers: ADD, SUB, AND, OR, XOR, NAND, NOR, and many others.5Block DiagramDFFAOI3333 (G, HS)XORControl Signals (ADD, OR, etc.)DFFHan-Carlson Carry Network8-bit Input8-bit Output6Function TableFUNCTION C7 C6 C5 C4 C3 C2 C1 C0 Z CINADD 0 0 0 1 0 1 1 0 1 XSUB 0 0 1 0 1 0 0 1 1 1AND 0 0 0 0 1 0 0 0 0 XOR 0 0 0 0 1 1 1 0 0 XNAND 0 0 0 0 0 0 0 1 0 XNOR 0 0 0 0 0 1 1 1 0 XXOR 0 0 0 0 0 1 1 0 0 XXNOR 0 0 0 0 1 0 0 1 0 XONES 0 0 0 0 1 1 1 1 0 XZEROS 0 0 0 0 0 0 0 0 0 XNOT A 0 0 0 0 1 1 0 0 0 XNOT B 0 0 0 0 1 0 1 0 0 X7Summary of Results•Determination of Gate Widths•Final schematic, and •Simulations: NC Verilog and SPICE•Final layout•Verification of layout and extraction.8Longest Path Calculations9Schematic - OverallAOI3333DFFHAN-CARLSON NETWORKXORDFFINVERTERBLACK CELLGPLONGEST PATH10Schematic & Layout – AOI333311Schematic & Layout – Black Cell12Simulation – NC Verilog - ADD13Simulation – NC Verilog - SUB14Simulation – NC Verilog - OR15Simulation – SPICE – Worst Case (Schematic)τPLH3.76ns16Simulation – SPICE – 2-bit Addition(Schematic)Input Output17Simulation – SPICE – Power Usage(Schematic)P = 25.28mW18Layout - OverallAOI3333DFFHAN-CARLSON NETWORKXORDFF19Verification – LVS Report20Cost Analysis•Estimated time spent on each phase of the project:–Verifying logic: 8 hours–Verifying timing: 10 hours–Layout: 45 hours–Post extracted timing: 8 hours ___________TOTAL: 71 hours21Lessons Learned•Start early.•Make sure that the overall logic works first (with actual transistors).•Once the overall timing is agreed upon, it’s hard to go back and make changes.•Use cell based design, it’s less confusing.•Save time for troubleshooting.22Summary•An 8-bit ALU which operates at a clock frequency of 200MHz was designed and simulated.•All specifications (clock and power) were met.23Acknowledgements•Dr. David Parent•Cadence Design Systems•Irma Alarcon (Lab
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