ECE 6450 - Dr. Alan DoolittleGeorgia TechTop View of a p-type waferIn Class Example of a “Simplified” Inverter Mask set: You probably will not want to print this file.Note: this example is meant to show effects of resolution and alignment only and is NOT the process used to produce most CMOS invertersECE 6450 - Dr. Alan DoolittleGeorgia Tech…open windows in oxide and add n-type wellIn Class Example of a “Simplified” Inverter Mask set: Probably will not want to print. Note: this example is meant to show effects of resolution and alignment only and is NOT the process used to produce most CMOS invertersECE 6450 - Dr. Alan DoolittleGeorgia Tech…open windows in oxide and add NMOS source/drainECE 6450 - Dr. Alan DoolittleGeorgia Tech…open windows in oxide and add PMOS source/drainECE 6450 - Dr. Alan DoolittleGeorgia TechDefine the gate oxideECE 6450 - Dr. Alan DoolittleGeorgia TechDefine the contact to the gateECE 6450 - Dr. Alan DoolittleGeorgia TechDefine Gate interconnectInECE 6450 - Dr. Alan DoolittleGeorgia TechOpen contacts to the source and drainInECE 6450 - Dr. Alan DoolittleGeorgia TechAdd source and drain interconnectsVdd Out In GndECE 6450 - Dr. Alan DoolittleGeorgia TechVdd Out In GndDrain not connected to channelSource overlapped to far into channelEffect of improper Registration (Source/drain PMOS Mask layer)ECE 6450 - Dr. Alan DoolittleGeorgia TechVdd Out In GndEffect of improper Registration (Source/drain PMOS Mask layer)Drain-channel width less than designed. Drain connected to substrate.Source-channel width more than designedECE 6450 - Dr. Alan DoolittleGeorgia TechAdd source and drain interconnectsVdd Out In GndEffect of improper Resolution (Gate contact window of NMOS Mask layer not resolved)NMOS Gate is left