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DREXEL CS 265 - The make Utility

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Slide 1Slide 2Slide 3Slide 4Slide 5Slide 6Slide 7Slide 8Slide 9Slide 10Slide 11Slide 12Slide 13Slide 14Slide 15Slide 16Slide 17Slide 18Slide 19Slide 20Slide 21Slide 22Slide 23Slide 24Slide 25Slide 26The make UtilityProgramming Tools and EnvironmentsWinter 2006makeThe make utility automates certain tasks (usually simple command-line stuff)compiling multi-file programsarchiving/extractinginstallationOften used to manage buildsruns the compiler only when necessaryuses file modify times to decide when it is necessaryMakefilesA basic makefile contains targetsA target consists of:Target name – file to be builtList of dependencies (if any)Command to build the targetRulestarget : dependenciescommand1command2…Each command executed in its own subshellEach command must start w/a tabThese MUST be tabs!!!Dependency ListA list of files that the target depends uponTarget is only built if it doesn't not exist, or if it exists, but is older than all of the dependencies.A dependency may also appear as a target in the same makefile; these are then intermediate targetsThis relationship is checked recursively, down the dependency treeSimple Examplelinecount : foo.c wc –l foo.c > linecountThis rule would tell make that the file linecount depends on the file foo.cTo build linecount the command “wc –l foo.c > linecount” should be runIf linecount doesn't exist, or foo.c is newer (modified more recently than linecount), the wc command will be executed(cont)$ maketarget maincheck dependencies, main.o & subs.o1. main.ocheck its dependenies, main.cc & subs.h2. subs.oetc.Does main exist? If so, is it newer than its dependencies?If no, execute command-lineInput FilesSpecify a makefile using the -f option to makemake -f myMakefileIf not specified, make looks in the current directory for (in order):1. makefile2. MakefileSimple Makefile for building a program.main: main.o subs.ogcc –o main main.o subs.osubs.o: subs.c subs.hgcc –c subs.cmain.o: main.c subs.hgcc –c main.cTABS!Make command line (simplified)make [options] [targets]options include “-f filename” use filename as the Makefile“-n” don’t do anything – just print what needs to be done.targets are what should be built (if needed).Specifying a targetJust specify the target after the make command:make subs.oIf no target is specified, the first target listed in the file is createdRevisit ExampleA target doesn't need dependencies, nor does its command-line need to make create the target:clean :- \rm *.o- \rm main $ make clean will cause those files to be removed (assuming there is no file called clean in the directory. See next slide.)Phony targets (GNU only)A target can be specified as phony, so that it is always executed:.PHONY : cleanclean :- \rm *.o- \rm mainThe dash in front of the commands tells make to ignore the return values; to continue executing, even if an error is returned.MacrosYou can create macros (make variables)OBJS = subs.o main.omain: $(OBJS)gcc –o main $(OBJS)Command ModifiersIf a command starts with @, it won't be echoed to stdout@echo “Hello thereA preceding - will tell make to ignore return statusclean: -\rm foo-\rm barFancy Stuff – Macro SubstitutionEvaluates to the value of a macro after some substitutions:SOURCE = main.c subs.cOBJS = ${SOURCE:.c=.o}now OBJS is main.o subs.oAutomatic Variables$@ Name of current target$< Name of first prerequisite$^ Name of all prerequisites, with spaces in between$? Name of all prerequisites newer than the targetSuffix RulesGeneral rules for building files that end with some suffix from files with the same name but a different suffixFor example, how to build a .o file from a .c file%.o : %.c$(cc) $< -o $@Example Suffix Rule.c.o:gcc –c $<This rule tells Make how to create a .o file any time is has a .c file (and needs the .o file to build a target).A Complete Example.c.o:gcc –c $<SOURCE = main.c subs.cOBJS = ${SOURCE:.c=.o}main: $(OBJS)gcc –o main $(OBJS)Comments and other Makefile notesComments begin with a ‘#’Can be placed at the beginning of a line or after a non-comment lineLines that are too long can be continued on the next line by placing a ‘\’ at the end of the first lineBasic Makefile exampleprogram : main.o iodat.o dorun.ogcc -o program main.o iodat.o dorun.omain.o : main.cgcc -c main.ciodat.o : iodat.cgcc -c iodat.cdorun.o : dorun.cgcc -c dorun.cSimplifying the example Makefile with macrosOBJS = main.o iodat.o dorun.oCC = /usr/bin/gccprogram : ${OBJS}${CC} -o $@ ${OBJS}main.o : main.c${CC} -c $?iodat.o : iodat.c ${CC} -c $?dorun.o : dorun.c ${CC} -c $?Simplifying the example Makefile againOBJS = main.o iodat.o dorun.oCC = /usr/bin/gccprogram : ${OBJS}${CC} -o $@ ${OBJS}Other useful Makefile tipsInclude a way to clean up your messclean:/bin/rm -f *.o coreInclude a target to build multiple programsall: program1 program2 program3EpilogueWe've looked at rather basic makefiles, but you already have a useful working knowledge.If you need it, make is capable of a good bit more. Read gnu's


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DREXEL CS 265 - The make Utility

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