305CS 701 Fall 2008©Reading Assignment• Read Assignment #3.306CS 701 Fall 2008©Automatic InstructionSelectionBesides register allocation and codescheduling, a code generator mustalso do Instruction Selection.For CISC (Complex Instruction SetComputer) Architectures, like theIntel x86, DEC Vax, and many specialpurpose processors (like Digital SignalProcessors), instruction selection isoften challenging because so manychoices exist.In the Vax, for example, one, two andthree address instructions exist. Eachaddress may be a register, memorylocation (with or without indexing),or an immediate operand.307CS 701 Fall 2008©For RISC (Reduced Instruction SetComputer) Processors, instructionformats and addressing modes are farmore limited.Still, it is necessary to handleimmediate operands, commutativeoperands and special case nulloperands (add of 0 or multiply of 1).Moreover, automatic instructionselection supports automaticretargeting of a compiler to a new orextended instruction set.308CS 701 Fall 2008©Tree-Structured IntermediateRepresentationsFor purposes of automatic codegeneration, it is convenient totranslate a source program into aLow-level, Tree-Structured IR.This representation exposestranslation details (how locals areaccessed, how conditionals aretranslated, etc.) without assuming aparticular instruction set.In a low-level, tree-structured IR,leaves are registers or bit-patternsand internal nodes are machine-levelprimitives, like load, store, add, etc.309CS 701 Fall 2008©ExampleLet’s look at howa = b - 1;is represented, wherea is a globalinteger variable andb is a local(frame allocated) integer variable.=aadr-*IntLiteral1+%fpboffset310CS 701 Fall 2008©Representation of InstructionsIndividual instructions can berepresented as trees, rooted by theoperation they implement.For example:*AdrReg →This is aninstruction thatloads a register withthe value at anabsolute address.Reg →+RegRegThis is an instruction that adds thecontents of two registers and stores thesum into a third register.311CS 701 Fall 2008©Using the above pair of instructiondefinitions, we can repeatedly matchinstructions in the following programIR:++***aadrbadrcadr++**badrcadr⇒Reg+*cadrReg+Reg*cadr+Reg+RegRegReg⇒⇒⇒⇒312CS 701 Fall 2008©Each match of an instruction patterncan have the side-effect ofgenerating an instruction: ld [a],%R1 ld [b],%R2 add %R1,%R2,%R3 ld [c],%R4 add %R3,%R4,%R5Registers can be allocated on-the-flyas Instructions are generated orinstructions can be generated usingpseudo-registers, with a subsequentregister allocation phase.Using this view of instructionselection, choosing instructionsinvolves finding a cover for an IR treeusing Instruction Patterns.Any cover is a valid translation.313CS 701 Fall 2008©Tree Parsing vs.String ParsingThis process of selecting instructionsby matching instruction patterns isvery similar to how strings are parsedusing Context-free Grammars.We repeatedly identify a sub-treethat corresponds to an instruction,and simplify the IR-tree by replacingthe instruction sub-tree with anonterminal symbol. The process isrepeated until the IR-tree is reducedto a single nonterminal.The theory of reducing an IR-treeusing rewrite rules has been studiedas part of BURS (Bottom-Up RewriteSystems) Theory by Pelegri-Llopartand Graham.314CS 701 Fall 2008©Automatic InstructionSelection ToolsJust as tools like Yacc and Bisonautomatically generate a string parserfrom a specification of a Context-freeGrammar, there exist tools that willautomatically generate a tree-parserfrom a specification of treeproductions.Two such tools are BURG (Bottom UpRewrite Generator) and IBURG(Interpreted BURG). Bothautomatically generate parsers fortree grammars using BURS theory.315CS 701 Fall 2008©Least-Cost Tree ParsingBURG (and IBURG) guarantee to finda cover for an input tree (if oneexists).But tree grammars are usually veryambiguous.Why?—Because there is usually morethan one code sequence that cancorrectly implement a given IR-tree.To deal with ambiguity, BURG andIBURG allow each instruction pattern(tree production) to have a cost.This cost is typically the size orexecution time for the correspondingtarget-machine instructions.316CS 701 Fall 2008©Using costs, BURG (and IBURG) notonly guarantee to find a cover, butalso a least-cost cover.This means that when a generatedtree-parser is used to cover (andthereby translate) an IR-Tree, the bestpossible code sequence is guaranteed.If more than one least-cost coverexists, an arbitrary choice is made.317CS 701 Fall 2008©Using BURG to SpecifyInstruction SelectionWe’ll need a tree grammar to specifypossible partial covers of a tree.For simplicity, BURG requires that alltree productions be of the formA → b (where b is a single terminal symbol) orA → Op(B,C, ...) (where Op is a terminal that is asubtree root and B,C, ... are non-terminals)A → Op(B,C, ...)denotesOpB C ...318CS 701 Fall 2008©All tree grammars can be put into thisform by adding new nonterminals andproductions as needed.We must specify terminal symbols(leaves and operators in the IR-Tree)and nonterminals that are used intree productions.319CS 701 Fall 2008©ExampleA subset of a SPARC instructionselector.TerminalsLeaf Nodesint32 (32 bit integer)s13 (13 bit signed integer)r (0-31, a register name)Operator Nodes* (unary indirection)- (binary minus)+ (binary addition)= (binary assignment)320CS 701 Fall 2008©NonterminalsUInt (32 bit unsigned integer)Reg (Loaded register value)Imm (Immediate operand)Adr (Address expression)Void (Null value)321CS 701 Fall 2008©ProductionsRule#Production Cost SPARC CodeR0 UInt → Int32 0R1 Reg → r 0R2 Adr → r 0R3 0R4 Imm → s13 0R5 Reg → s13 1mov s13,RegR6 Reg → int32 2sethi%hi(int32),%g1or %g1,%lo(int32),RegR7 1sub Reg,Reg,RegAdr →+Reg ImmReg →−Reg Reg322CS 701 Fall 2008©R8 1sub Reg,Imm,RegR9 1ld [Adr],RegR10 2sethi%hi(UInt),%g1st Reg,[%g1+%lo(Uint)]Rule#Production Cost SPARC CodeReg →−Reg ImmReg →∗AdrVoid →=UInt Reg323CS 701 Fall 2008©ExampleLet’s look at instruction selection fora = b - 1;where a is a global int, accessed witha 32 bit address andb is a local int,accessed as an offset from the framepointer.=int32-*s13+r s13324CS 701 Fall 2008©We match tree nodes bottom-up.Each node is labeled with thenonterminals it can be reduced to, theproduction used to produce thenonterminal, and the cost to generatethe node (and its children) from thenonterminal.We match