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MIPS R10000 MicroprocessorUser’s ManualVersion 2.0Version 2.0 of October 10, 1996 MIPS R10000 Microprocessor User's Manual viii Table of Contents1Introduction to the R10000 ProcessorMIPS Instruction Set Architecture (ISA).....................................................................................2What is a Superscalar Processor?.................................................................................................3Pipeline and Superpipeline Architecture..........................................................................3Superscalar Architecture.....................................................................................................3What is an R10000 Microprocessor?............................................................................................4R10000 Superscalar Pipeline...............................................................................................5Instruction Queues...............................................................................................................6Execution Pipelines..............................................................................................................664-bit Integer ALU Pipeline......................................................................................6Load/Store Pipeline...................................................................................................764-bit Floating-Point Pipeline...................................................................................7Functional Units ...................................................................................................................9Primary Instruction Cache (I-cache)..................................................................................9Primary Data Cache (D-cache)...........................................................................................9Instruction Decode And Rename Unit..............................................................................10Branch Unit ...........................................................................................................................10External Interfaces................................................................................................................10Instruction Queues.........................................................................................................................11Integer Queue .......................................................................................................................11Floating-Point Queue...........................................................................................................11Address Queue.....................................................................................................................12Program Order and Dependencies..............................................................................................13Instruction Dependencies....................................................................................................13Execution Order and Stalling .............................................................................................13Branch Prediction and Speculative Execution .................................................................14Resolving Operand Dependencies.....................................................................................14Resolving Exception Dependencies...................................................................................15Strong Ordering....................................................................................................................15An Example of Strong Ordering..............................................................................16R10000 Pipelines.............................................................................................................................17Stage 1....................................................................................................................................17Stage 2....................................................................................................................................17Stage 3....................................................................................................................................18Stages 4-6...............................................................................................................................18Floating-Point Multiplier (3-stage Pipeline)...........................................................18Floating-Point Divide and Square-Root Units.......................................................18Floating-Point Adder (3-stage Pipeline) .................................................................18Integer ALU1 (1-stage Pipeline)...............................................................................18Integer ALU2 (1-stage Pipeline)...............................................................................18Address Calculation and Translation in the TLB..................................................19Implications of R10000 Microarchitecture on Software............................................................20MIPS R10000 Microprocessor User's Manual Version 2.0 of October 10, 1996 11. Introduction to the R10000 ProcessorThis user’s manual describes the R10000 superscalar microprocessor for the systemdesigner, paying special attention to the external interface and the transferprotocols.This chapter describes the following:• MIPS ISA• what makes a generic superscalar microprocessor• specifics of the R10000 superscalar microprocessor• implementation-specific CPU instructionsVersion 2.0 of October 10, 1996 MIPS R10000 Microprocessor User's Manual 2 Chapter 1.1.1 MIPS Instruction Set Architecture (ISA)MIPS has defined an instruction set architecture (ISA), implemented in thefollowing sets of CPU designs:• MIPS I, implemented in the R2000 and R3000• MIPS II, implemented in the R6000• MIPS III, implemented in the R4400• MIPS IV, implemented in the R8000 and R10000The original MIPS I CPU ISA has been extended forward three times, as shown inFigure 1-1; each extension is backward compatible. The ISA extensions areinclusive; each new architecture level (or version) includes the former levels.†Figure 1-1 MIPS ISA with ExtensionsThe practical result is that a processor implementing MIPS IV is also able to runMIPS I, MIPS II, or


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MTU EE 4173 - MIPS Microprocessor

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