Physics 111 – BSC Lecture 11 Page 1 of 7 Jim Siegrist Phone: 486-4397 Email: [email protected] Room (at LBL): 50-4055 Advice: Today: lec 11 Digital II lec 12 TUE Apr 3 Digital III Posted solutions, lab 3 & 4 Final project proposals due April 7 – see TA’s (I sign) Problems 8.12, 8.13 → supplementary. Concepts Digital Circuits Digital Signals are required to be within one of 2 ranges – ‘HI’ & ‘LO’. What the range is depends on the type of logic – more later. ‘It’s all just 1’s & 0’s’ bit ≡ binary digit Rate at which bits can be transferred by a digital system determines its speed (≡ baud = bit/sec) (gigabit easily achievable) Other voltage levels appear during switching, and sometimes when outputs are not in use, but such levels are undefined. Logic Building Blocks - combinational logic several inputs, one output output at a given time depends on inputs at same time - sequential logic output depends on what inputs are now & at earlier times (flip-flop) any voltage in here 1≡≡HIany voltage in here 0≡≡LOPhysics 111 – BSC Lecture 11 Page 2 of 7 =negation≡Combinational Logic Examples Inputs Output A B C 0 0 0 0 1 1 1 0 1 OR gate: Truth Table 1 1 1 Output is HI if & only if one or more of the inputs is high. (3 input truth table would have 8 entries) Inputs Output A B C 0 0 0 1 0 0 0 1 0 AND gate: 1 1 1 Output HI if & only if all inputs are HI Input Output A B 0 1 Inverter (Complement): 1 0 ⇒ NAND gate Inputs Output A B C 0 0 1 1 0 1 0 1 1 Also see circles on input sometimes: 1 1 0 ABCABCABPhysics 111 – BSC Lecture 11 Page 3 of 7 Exclusive OR A B C 0 0 0 1 0 1 0 1 1 1 1 0 output true if one and only one input is true NOR: Logic Notation & Boolean Algebra Complement A OR A + B AND A ⋅ B Two logical expressions are equivalent if their truth tables are the same. 0 + 0 = 0 0 ⋅ 0 = 0 0 + 1 = 1 + 0 = 1 0 ⋅ 1 = 1 ⋅ 0 = 0 1 + 1 = 1 1 ⋅ 1 = 1 01,10 == De Morgan’s Theorem e.g. X Y X + Y YX+X Y YX⋅0 0 0 1 1 1 1 1 0 1 0 0 1 0 0 1 1 0 1 0 0 1 1 1 0 0 0 0 ABC()()()()BAABBABABABABABA⋅+⋅=+⋅+=⋅⋅+=⋅++≡()tablestruthofcomparisonbyproveYXYXYXYX⎪⎭⎪⎬⎫+=⋅⋅=+Physics 111 – BSC Lecture 11 Page 4 of 7 Note distributed law also satisfied: A ⋅ (B + C) = A ⋅ B + A ⋅ C e.g., mathematical algebra A B C B + C A ⋅ (B + C) A ⋅ B A ⋅ C A ⋅ B + A ⋅ C 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 1 1 1 0 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 Logic Design Achieve a specified truth table with least possible number of gates. Use Boolean algebra rules to simplify logic expressions. Coding & Decoding – binary number representation How do I represent a decimal number in binary? Set of m binary number has up to 2m distinct values. 10 possible values for a decimal digit ⇒ 24 = 16 > 10 bits required (8 bits = 1 byte; 4 bits ≡ nibble) Frequently, write bytes in Hex. 0–9ABCDEF Concepts Sequential Logic (flip-flops) Most common sequential logic circuit – bistable multivibrator – exists in (≡ flip-flop) one of 2 stable states (HI or LOW) (other multivibrators – monostable – returns to same state astable – oscillator) Flip-Flop types: S-R, J-K, D S-R Flop (set, reset) S R Qn Qn+1 0 0 0 0 keep Q value {0 0 1 1 0 1 0 0 reset {0 1 1 0 1 0 0 1 set {1 0 1 1 SRQ don’t use,meaningless→1 1 S, R both low ⇒ block ‘remembers’ Q To set Q, use S = 1, R = 0; to ‘reset’ use S = 0, R = 1Physics 111 – BSC Lecture 11 Page 5 of 7 Circuit Analysis Circuit Realization: S R Qn Qn+1 0 0 0 0 0 0 1 1 } same state 1 0 0 1 1 0 1 1 } set 0 1 0 0 0 1 1 0 } reset Concepts D flip-flop Flip-flop only changes state when a ‘change’ instruction is given (clock ‘CK’ input). CK changes from 0 – 1 (makes a positive transition) ⇒ Q = D (Q set to D) D Qn Qn+1 0 0 0 0 1 0 1 0 1 1 1 1 D edge-triggered flip-flop Also, master-slave version: Data sampled while CK HI, ‘latched’ when CK goes LO. SRQQDCKQQPhysics 111 – BSC Lecture 11 Page 6 of 7 Circuit Analysis Logical circuit realization. D-type, positive edge-triggered. CK LO ⇒ X = Y = HI → ⇒ Q, Q outputs stable CK HI enables 2 & 3 ⇒ D D Qn Qn+1 0 1 ⎯ 0 ⎯ At edge: →⎭⎬⎫→∗→∗YDXD ‘latched’ by output at this point After 1 prop delay: (CK now HI) 1 → false ()0=⋅ DD ⇒ 2 → HI ⇒ X → HI 4 → false ()0=⋅ DD ⇒ 3 → HI ⇒ Y → HI X HI, Y HI = back to initial condition, CK goes LO & output is stuck. 123456CKDHDLH→HYXDLH→HDDDDDHHHHHLLQQDPhysics 111 – BSC Lecture 11 Page 7 of 7 Circuit Analysis Logical Circuit Realization, D flip-flop Operation: CK HI 1 & 2 enabled ⇒ master-slave version - master flip-flop gets same state as D input (gates 3 & 4) - gates 5 & 6 disabled, so output stable CK goes LO inputs to master don’t see D input, inputs of slave come from master ⇒ master transfers its state to slave - master stuck, so no output changes e.g. J-K flop (like D, but 2 inputs) J K Qn+1 0 0 Qn 0 1 0 1 0 1 1 1 nQ (reverse state after each clock pulse) Jam set & reset also common: CKD12345678QQmmmasterslaveDCK1234mHH HH HHH HLLLLLLditto forslave sectionCKKJQSR⇒edge