Physics 623Programmable Gate Array ExperimentNov. 30, 20061 The Goal of This ExperimentYou will design a small digital circuit, download the design to a Field Programmable Gate Array(FPGA) IC, and verify that the circuit operates as predicted.When using an FPG A, you build the circuit by creating the circuit diagram with schematiccapture software and then running programs that creates a bitmap that is downloaded into theFPGA chip. This technique is valuable, in research or any enterprise, since you can quickly makemoderately complex circuits and yet quickly make changes as the needs change.2 Xilinx FPGA IntroductionA Field Programmable Gate Array, commonly known as an FPGA, is a general purpose pro-grammable IC which is mainly used in the digital design environment that requires flexibility indesign and fast turn around time.In contrast to design using commercial ICs, FPGA can be configured to the designer’s specificcircuits in a single chip. In addition, in the case of design errors, FPGA can be redesignedand reconfigured easily in software, where as in the commercial IC design, it is not so easy tomodify the already connected circuitry. In comparison to EPLD (Electrically ProgrammableLogic Device), FPGAS have more levels of registers and a more general routing topology. Thisrenders the EPLD less useful in more general systems, especially in pipelined systems. Becauseof its size, ease of use, and reconfigurability, FPGA represents an attractive alternative in digitaldesign. It is particularly suitable for experimental and rapid prototyping environments. Differenttypes of FPGA from different vendors are available. The one we will be using is the Xilinx FPGA.Therefore, throughout this document, the term FPGA is referring to the Xilinx FPGA.In general, there are two kinds of blocks in a Xilinx FPGA: Configurable Logic Blocks (CLB)and Input/Output Blocks (IOB). Each CLB is capable of supporting generic combinational logicfunctions and is composed of Look-Up tables, Carry and Control Logic and D-type flip-flopstorage elements. Each FPGA contains a good number of CLBs arranged in a 2-dimensionalsquare array to implement and interconnect the desired logic functions of the system. In theSpartan II XC2S50 containing 50,000 logic gates, there are 384 CLBs arranged in a 16 by 24array.IOBs are used to support the interface, including TTL voltage level, higher driving current,3-state buffers, etc..., to the external environments. In addition, one flip-flop is also available ineach IOB to provide latched input/output. Depending on the size of the chip, different size ofFPGA contains different number of IOBs placed on the perimeter of the CLB array. In the caseof XC2S50, there are 92 IOBs available for external connections.Configurable routing wires are presented between CLBs and between CLBs and IOBs forinterconnecting blocks. The routing wires are arranged in the form of a configurable matrix suchthat connections from any direction to any other direction are possible.The Xilinx FPGA design process consists of the following procedures:12.1 FPGA Design Flow• The Schematic Capture tool is used for the design entry of the circuit.• The Design Implementation tools perform the translation, map, place, route and bitstreamgeneration phases of the design flow.• The binary image of the circuit design is downloaded to the FPGA chip using a Downloadtool.3 Experimental ProceduresThis experiment is to acquaint you with the design process of Xilinx FPGA. You will enter thedesign of a simple circuit for the FPGA, download it to the FPGA, and verify that it works inhardware.The CAD tool for drawing the circuit schematic is integral to the Xilinx Integrated SoftwareEnvironment (ISE 6.1) software that runs on Windows platorms.The FPGA chip you will be using is the Spartan II XC2S50. It contains 384 CLBs arrangedin a 16 by 24 array. In addition, there are 92 user I/Os available for external connection.The first circuit with which we will implement is a four bit synchronous binary count-upcounter. The first step with any circuit is to check the logic of the circuit and understand how itworks.4 EquipmentThe experiment uses the following equipment.• A test board (XSA-50) which contains the XC2S50 Sparten II Xilinx FPGA, readout de-vices, and input/output cable connectors.• A motherboard (XStend) for the test board that contains more readout devices, switches,analog I/O, a keboard and VGA interface, and a prototyping area in which additionalcircuit components can be added.• An Windows XP PC with the Xilinx development software.• Stabilized voltage supply of +9.0 Volts that plugs into the test board.• An oscilloscope.5 Design ProcessIt is assumed that you already know how to draw and edit a schematic using CAD schematiccapture tools.• Log on to the PC. The instructor will supply the login password if needed.2• Under the Xilinx program Group, start the Project Navigator. The Project Navigatorcontrols all aspects of the design flow. You can access all of the design entry and designimplementation tools as well as the files and documents associated with your project. Createa new project by selecting File → New Project Item.• Under Project Location select a folder for your project files. Make a folder for yoursef inthe Student directory. (C:\623Students\YourFolder) Set the project name in the ProjectName field and select Schematic as the Top-Level Module.• Choose the appropriate family, part, and speed grade. This operation w ill load the ap-propriate part libraries. Use the Spartan2 xc2s50 with package tq144 and speed grade -5.Keep clicking Next until Finish shows up and then click on it.• Right click on the xc2s50-stq144 object and select New Source. Select Schematic.• Click on the Symbols button to bring up the Parts library. Click on the desired part, movethe mouse over to the schematic window and click again. The part will then be enteredinto the schematic window and will clone itself. Right mouse click to terminate the entryfor that part. Enter all the desired parts.• Unlike Electronics Workbench, wires or buses must be added by using the wire tool.• After the circuit is complete I/O markers must be added to designate inputs and outputsand later to assign them to real pin numbers. Click on the I/O markers button and selectadd and output marker or add an input marker in the Options tab. Then click on the freeend of the wire segment to place the marker. Note the names assigned to