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Rice ELEC 326 - Study Notes

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ELEC 326: Class projectKartik Mohanram1 IntroductionFor this project you will design and test a three-digit binary-coded-decimal (BCD) adder capable of addingpositive and negative BCD numbers. In the process, you will1. gain experience with modern CAD techniques used to design digital systems,2. gain experience with designs that require ad-hoc design techniques,3. learn to test projects through simulation,4. learn to download projects to an FPGA board and perform physical testing, and5. learn about BCD addition and subtraction.1.1 Project Behavioral SpecificationThe BCD adder you design must be capable of adding two three-digit BCD operands to produce a three-digitsum. Each of the two operands can be either positive or negative, so the adder must, in effect, be capable ofboth addition and subtraction. The operands and sum are represented by 13-bit binary vectors where 12 ofthe bits are the three 4-bit BCD digits and the 13th bit is a sign bit (0 if the number is positive and 1 if it isnegative). This is essentially a sign-plus-magnitude representation where the magnitude is represented withthe BCD code. The adder should also have a one-bit overflow output signal that is 1 if the addition results inan overflow (a magnitude that is too big to be represented with 3 BCD digits) and 0 otherwise. BCD codesand arithmetic are discussed in Example 2.10 and Section 5.2 of the textbook. Recall, however, that Verilogallows you the great ‘+’ operator that abstracts the details and makes design easy!1.2 Project OrganizationThe adder is to be organized as three identical digit-adders connected in a ripple-carry configuration. Each ofthe digit-adders will be capable of adding two 4-bit BCD digits and a 1-bit carry/borrow input to produce a4-bit BCD sum and 1-bit carry/borrow output. The adder should implement the following general algorithm:1. The adder checks the signs and relative magnitude of the two operands.2. If signs are the same, the adder adds the operands and makes the sign of the result equal the signs ofthe operands.3. If the signs differ, then the adder compares the magnitudes of the operands, subtracts the smaller fromthe larger, and sets the sign of the result equal to the sign of the larger. Note that if the result is 0, thesign of the result must be positive (0 sign bit).1A high-level block diagram for the project is given in Figure 1. It shows the main data flow paths thatconnect the modules, but does not show the signals that connect to the control unit. That module will needinputs from the other modules and will generate control signals for all the modules. Part of the projectassignment is to figure out what these control signals should be. The block diagram also shows how theswitches and displays on the FPGA board are used. The remainder of this section describes the behavior ofthe modules in this diagram.DIGITADD: This is a digit adder that takes two 4-bit BCD numbers and a carry/borrow input and producesa 4-bit BCD sum or difference and a carry/borrow output.SSCTLR: This is the seven-segment display controller. It takes three 4-bit BCD numbers and displays themin the right three digits of the display. It also displays the sign in the leftmost digit position. The sign digitshould turn on only the middle segment (minus sign) when the result is negative. When the result is positive,all segments on the fourth digit should be off.REGUNIT: This module contains two 4-bit registers that hold the input operands for the DIGITADD mod-ule. There are not enough switches on the FPGA board to bring each input digit from a switch, so BCD inputdigits must be entered sequentially, one at a time, into the REGUNIT registers. This unit is also responsiblefor swapping the operands when necessary because the available adders can only subtract the B input fromthe A input, not the other way around. It is also convenient to add logic to the REGUNIT to determine whichof the input operands is larger (needed to determine if the operands must be switched). The logic for thisshould be designed so that when several REGUNIT modules are connected in series, they will determinewhich of the 3-digit BCD numbers is larger (or whether they are equal).CTLUNIT: This module takes information from the other modules and generates the control signals forthose modules. It must check the signs and magnitudes of the operands and decide whether to do an additionor subtraction and whether to swap the operands. It is also responsible for computing the sign of the result.SWITCHES and DISPLAYS: Operands are entered through five toggle switches (4 for the magnitude and1 for the sign). The 4-digit, seven segment display shows both the sign and magnitude of the result. OneLED is used to indicate an overflow. One toggle switch (ABSEL) indicates which of the two operands (Aor B) is being loaded. Another toggle switch (SHOWREG) indicates whether the output display shows thevalue stored in one of the operand registers or the output of the adders. If a register operand is displayed,the ABSEL switch determines which one. One push-button switch clears all the registers to 0. Anotherpush-button causes the next digit to be loaded in the registers.2 Project ImplementationThis section gives some more detailed information about how to implement the modules in the block diagramabove. Each of the modules should be implemented as a Verilog module.2.1 DIGITADDProbably the best way to implement the digit adder is by first doing a binary addition/subtraction andthen correcting the sum, if it is outside the range of valid BCD digits (i.e., greater than 9). The cor-rection can be implemented by adding a correction value to the intermediate result produced by the firstaddition/subtraction. You can implement this with a 4-bit binary adder/subtractor to do the first addi-tion/subtraction and another binary adder to perform the correction. You must determine when to do the2corrections and what correction values to add. You will need logic to generate the correction value.2.2 REGUNITYou should implement the registers in this module so that when the three REGUNIT modules are connectedtogether, the three A operand registers form a 4-bit wide shift register and the three B operand registers formanother shift register. These shift registers should shift from the least significant digit to the most significantdigit. Connect four of the data entry toggle switches to the least significant position of both of these shiftregisters and use the ABSEL switch


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