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Nano Decoders

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IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 2, NO. 3, SEPTEMBER 2003 165Stochastic Assembly of SublithographicNanoscale InterfacesAndré DeHon, Member, IEEE, Patrick Lincoln, and John E. Savage, Life Fellow, IEEEAbstract—We describe a technique for addressing individualnanoscale wires with microscale control wires without usinglithographic-scale processing to define nanoscale dimensions.Such a scheme is necessary to exploit sublithographic nanoscalestorage and computational devices. Our technique uses modula-tion doping to address individual nanowires and self-assembly toorganize them into nanoscale-pitch decoder arrays. We show thatif coded nanowires are chosen at random from a sufficiently largepopulation, we can ensure that a large fraction of the selectednanowires have unique addresses. For example, we show thatlines can be uniquely addressesd over 99% of the time usingno more than2 2log2( ) +11address wires. We furthershow a hybrid decoder scheme that only needs to address=(litho pitch nano pitch)wires at a time through this sto-chastic scheme; as a result, the number of unique codes requiredfor the nanowires does not grow with decoder size. We give an(2)procedure to discover the addresses which are present.We also demonstrate schemes that tolerate the misalignment ofnanowires which can occur during the self-assembly process.Index Terms—Bootstrapping, electronic nanotechnology, molec-ular electronics, nanoscale interfacing, stochastic assembly.I. INTRODUCTIONRECENT developments demonstrate that we can buildcarbon nanotubes (CNT) [1] and semiconducting nano-wires (NW) [2], [3] that are just a few nanometers in diameter.Furthermore,ithasbeenshownthatself-assemblytechniquescanbe used to produce sets ofparallelNWswithnanometerspacing.One set can then be placed above another at right angles [4], [5].The crosspoints in these arrays can act as nonvolatile switchingelements [6], [7], allowing us to control and differentiate thebehavior of the assembled arrays at the nanoscale. Technologyof this kind may form the basis for nanoscale memory devicesand even programmable nanoscale logic arrays [8].Remarkably, the dimensions of these nanoarrays (diameter ofthe wires, spacing between wires) are controlled to nanometerdimensions without using direct lithographic patterning [9].Molecular seed catalysts control the diameter and physicalforces between wires control spacing.Manuscript received April 28, 2003; revisedJune 1, 2003. This work was sup-ported by the Defense Advanced Research Projects Agency Moletronics Pro-gram under Grant ONR N00014–01-0651 and by the National Science Founda-tion under Grant CCR-0210225.A. DeHon is with the Department of Computer Science, California Instituteof Technology, Pasadena, CA 91109 USA (e-mail: [email protected]).P. Lincoln is with the Computer Science Laboratory, SRI International, MenloPark, CA 94025 USA.J. E. Savage is with the Department of Computer Science, Brown University,Providence, RI 02903 USA.Digital Object Identifier 10.1109/TNANO.2003.816658Fig. 1. Decoder bridging between microscale and nanoscale wires (not shownto typical scale); the decoder arrangement allows a small number of microscalewires to address any single nanoscale wire in a large array.This leaves a critical weak link in our path to the constructionof fully nanoscale memory and logic arrays: constructing theinterface that allows us to individually address these nanoscalewires from our conventional, microscale wires. We must be ableto control single NWs individuallyso that individual crosspointscan be programmed and addressed.In this paper, we propose an address decoder that usesa small number of microscale control wires to selectivelyactivate one of a large number of NWs as suggested in Fig. 1.Differently coded modulation-doped NWs (Section III) providethe independent NW addressability. Our address decoder canbe assembled without relying on lithographic patterning atnanoscale dimensions by randomly mixing differently codedNWs and enabling them to self-assemble (Section V) into a par-allel array at right angles to a pre-existing array of microwiresusing previously demonstrated flow and Langmuir–Blodgetttechniques. This approach realizes a microscale-to-nanoscaleinterface, bridging the gap from top-down lithographic pro-cessing to bottom-up self-assembly. The differently codedmodulation-doped NW-based address decoder is robust: Itovercomes misalignment of NWs (Section VI), allows thecustomization of nanoscale programmable computing arrays topersonalize behavior and tolerate faults, and directly enablesreliable nanoscale memory devices (Section VII). We candiscover the codes present in such a decoder with reasonableefficiency (Section VIII).1536-125X/03$17.00 © 2003 IEEE166 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 2, NO. 3, SEPTEMBER 2003Fig. 2. NW FETs with multiple gated wire crossings serve as an AND, allowingsignal flow only when all control wires have suitable voltages.II. PRIOR WORKTo date, only one other scheme has been proposed to ad-dress this microscale–nanoscale interface problem [10]. Kuekesand Williams describe a scheme for bridging the microscale–nanoscale gap with a decoder based on randomly deposited goldnanoparticles. The gold particles must be deposited over the re-gion in which control and address wires intersect. The approachrelies on close control of the density of deposited particles, ide-ally targeting half of the points of intersection. Additionally,the approach relies on strongly quantized connection values foreach intersection, while imprecisely localized gold nanoparti-cles could lead to intermediate values that complicate the dis-covery approach. Consequently, the Kuekes and Williams ap-proach comes with its own set of manufacturing challenges.Our addressing scheme offers tighter address encoding, re-quires fewer novel processes, and uses standard semiconductorindustry materials and dopants.III. MODULATION-DOPED CODED NWSDoped NWs act as field-effect transistors (FETs) [11], thatis, conduction along the length of an NW can be controlledby an applied voltage field. For the depletion-mode p-type de-vices demonstrated to date, a lowvoltage (or no applied voltage)will allow good conduction, whereas a high applied voltagewill evacuate carriers from the doped semiconductor, preventingconduction along the NW length. This allows us to build a com-bining logic when several conductors cross a doped NW—if allthe inputs are low, there is a conduction


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