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PRIMITIVES FOR THE CMS CATHODE STRIP MUON TRIGGERJ. Hauser, University of California, Los Angeles, USA (email: [email protected])AbstractThe endcap muon detector for CMS uses Cathode StripChambers (CSCs) to deliver precise muon position and timinginformation in a high background rate environment[1]. Triggerelectronics for this system need to reliably identify the bunchcrossing in spite of drift times spanning several crossings, andneed to precisely measure the muon bend plane coordinate ineach station to allow momentum measurement in spite of limitedmagnetic bending power. Prototypes were placed in test beams atCERN in the summers of 1998 and 1999. Results from these testson pattern identification, timing efficiency, and spatial resolutionare presented. Plans for future developments are also described.1. CMS ENDCAP MUON CSC SYSTEMBefore discussing the details of the electronics, it is useful toreview the general layout of the Cathode Strip Chamber systemused in the CMS Endcap Muon detector. This detector is plannedfor 4 stations, however, at present construction money for only 3stations is assured. There are 432 CSC chambers, each 10- or 20-degree trapezoidal 6-layer chambers in the 3-station detector asshown in Figure 1.Figure 1 CSC stations for one of the CMS endcaps. The irondisks between the stations are not shown. In each of the six layers of a chamber, some 1000 anode wiressupply gas amplification. Charges on orthogonal radial strips areread by precision electronics and are used offline for precisionposition measurement in the solenoid bend plane, i.e. the φcoordinate. Since the wire signals are larger, they are amplifiedby faster electronics and are mainly used to indicate the 25nsLHC bunch crossing from which a muon came.2. CSC TRIGGER PRIMITIVESSimulations indicate that at maximum luminosity, severalbackground clusters exist within each CSC at any given time. Toreduce the otherwise huge background rate, CSC triggerprimitives are formed from the spatial coincidence of clusters inthe 6 layers of the chamber.The cathode strip cluster position is determined for triggeringto one-half of a strip width in each layer[2]. This is done with a16-channel 'comparator' ASIC that inputs amplified and shapedsignals and compares the charges on all adjacent and next-to-adjacent strips. If a strip charge is found to be larger than thoseon its neighbors, a hit is assigned to the strip. Also, comparisonof left versus right neighbour strip charges allows assignment ofthe hit to the right or left side of the central strip, effectivelydoubling the resolution. The six layers are then brought intocoincidence in 'Local Charged Track' (LCT) pattern circuitry (seeFigure 2) to establish position of the muon to an RMS accuracyof 0.10-0.15 strip widths. Strip widths range from 6-16mm.Because of the slow 150ns rise-time of the cathodeamplifier/shapers, the cathodes cannot uniquely identify thebunch crossing.The anode wires are ganged 10-15 to a group, and their signalsare fed into amplifier/constant-fraction discriminators. Since thedrift time can be as large as 50ns, a multi-layer coincidencetechnique in the anode LCT pattern circuitry is used to identifythe bunch crossing. For each spatial pattern of anode hits, a lowcoincidence level, typically 2 layers, is used to establish timing,whereas a high coincidence level, typically 4 layers, is used toestablish the existence of a muon track. The algorithm isillustrated in Figure 2.Figure 2 Algorithms for trigger primitives for cathodes andanode planes of CSC chambers.3. 1998 PROTOTYPES AND RESULTSElectronics prototypes were tested on a full-size prototype ofthe largest CSC chamber in the summer of 1998 at CERN. Testswere done first at the H2 beam line, where a Silicon beamtelescope was used for resolution studies. Later tests were done atthe GIF (Gamma Irradiation Facility), where LHC-likebackgrounds were provided by an intense gamma source. Thechamber is shown at the H2 beam line in Figure 3.Figure 3 CSC chamber in the CERN H2 beam line duringSummer 1998.3.1 Cathode Comparator ASIC TestsThe 16-channel cathode comparator ASICs that were testedduring summer 1998 had 32 half-strip output bits. Six of thesechips were mounted on a 96-channel comparator board (Figure 4)that attached directly through connectors to the cathode front-endboard. The 192 half-strip bits were converted from TTL levels todifferential LVDS and 96 of these signals were driven on cablesto a cathode LCT card in a CAMAC crate, where they wererecorded.Figure 4 Comparator ASICs (center) mounted on thecomparator board used in 1998 tests.The efficiency of the comparator ASICs for identifying thecorrect half-strip was determined in two ways. First, the half-stripbits were compared to bits predicted by the precision chargedetermination of the front-end DAQ cards[3]. These cardsemploy switched-capacitor arrays (SCAs) for charge storage, andADCs for digitization. Typical noise levels on the DAQ datawere 1.6fC (1.6mV after the amplifier/shapers), while typicallythe total cathode charge read out was 100fC. The efficiency wasfound to be 90.4±0.2% for exact half-strip match, while a matchwindow of ±1 half-strips yielded an efficiency of 98.3±0.1%. Thesecond way to determine the comparator match efficiency is lessbiased but gives lower statistics. This method uses the precisionDAQ data to track muons through the chamber, leaving out onelayer (#3) from the fit. The extrapolated position in this layer isthen compared to the half-strip bit found by the comparatorASIC. By this method, the efficiency for exact match is measuredto be 88.2±0.7% for exact half-strip match, while a widenedmatch window of ±1 half-strips yields an efficiency of94.9±0.4%.3.2 Cathode LCT TestsThe half-strip bits found by the comparator ASICs were sent tothe cathode LCT card (Figure 5), which identified the multi-layerpatterns of valid muon trajectories. A mezzanine card convertedLVDS signals to TTL levels. These signals were distributed by a"front" Altera 10K50 FPGA to Cypress 128Kx8bit SRAMs,which found the patterns, while a "rear" Altera 10K20 FPGAcollected the patterns (if any) found by the SRAMs and selectedthe best according to pattern number. Higher numberscorresponded to larger numbers of hit layers and straighter tracks.The CAMAC interface was implemented in another Altera10K20 FPGA. Output trigger information was fed through aNational Instruments Channel-Link to a "Trigger Motherboard"which sorted LCTs


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