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NYIT EENG 494 - HDL Design Principles for VLSI/FPGAs

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EEGN-494 HDL Design Principles for VLSI/FPGAsIntroduction to VerilogVerilog Vs VHDLSyntax used in describing a moduleContinuous assignmentInitial blockAlways blockModule instantiation (by position)Module instantiation (connectivity by name)Data ObjectsRegistersRegisters and PortsNumbersDescription of a flip flopDescription of a flip flop with asynchronous reset_nArithmetic operatorsRelational OperatorsEquality OperatorsLogical OperatorsBit-wise operatorsfor loop synthesisBasic Verilog fileSlide 23Kazi Fall 2006 EEGN 494 1EEGN-494HDL Design Principles for VLSI/FPGAsKhurram Kazi2Kazi Fall 2006 EEGN 494Introduction to VerilogPresent day ASIC/FPGA designers most likely have to work with VHDL and Verilog in one form or another. People who used VHDL mostly, are likely to encounter Verilog as the language that describes the gate level netlist.Good to know both HDLs.Both have their strong points and have weaknesses.3Kazi Fall 2006 EEGN 494Verilog Vs VHDLVerilog is perceived to be loosely typed language.VHDL strongly typed language.Fact of the matter is that ones choice of VHDL over Verilog or vice versa most likely tends to be based ones familiarity with either of the languages or company’s past history of development platform.Both languages serve as an excellent tool for RTL development.Neither of them is well suited for the verification of complex ASICs especially that are algorithmic intensive. Languages like specman ‘e’, Synopsys “vera” or C/C++ have become the languages of choice for verification platform.4Kazi Fall 2006 EEGN 494Syntax used in describing a module Module is a fundamental block in Verilog that is synonymous to entity. Verilog does not support different architectures for the same entitymodule <module name> (port list); <declarations> <module items>endmodule5Kazi Fall 2006 EEGN 494Continuous assignmentThis is synonymous to concurrent block statement in VHDL// get continuously updated whenever any of the input operands// change value.module new_or ( a b c);input a;input b;output c; assign c = (a | b); // using & would have performed and functionendmodule6Kazi Fall 2006 EEGN 494Initial block// Initial block consists of a statement or a group of statements enclosed in a begin and // end which will be executed only once at simulation time 0. If there is more than one // initial block they get executed concurrently independent of each other. Normally used // for initializing, monitoring, generating clocks etc.module stimulus1initial reset_n = 1’b0;#25 reset_n = 1’b1;initial begin // multiple statements have to be lumped together variable1 = 0; #10 variable1 = 1; #10 variable1 = 0 #30 variable1 = 1; #50 variable1 = 0;end;7Kazi Fall 2006 EEGN 494Always block// statements in the “always” block repeatedly get executed until the simulation is// stopped by $finish or $stop. Similar to a process in VHDL// Block that generates a clockmodule clk_genreg clk; Intial begin clk = 1’b0; // setting the initial value of the clock endalways begin #25 clk = ~clk; // clock repeating every 50 time units endIntial begin #5000 $finish; // simulation ends after 5000 time units endendmodule clk_gen8Kazi Fall 2006 EEGN 494Module instantiation (by position)module couple_of_ands ( a, b, c, d);input a;input b;input c;output dwire w1;// two instances of the module testandstestands and1 (a, b, w1); // assuming the 1st two ports are inputs and 3rd // is the output of the and gatetestands and2 (w1, c, d);endmodule9Kazi Fall 2006 EEGN 494Module instantiation (connectivity by name)module mux4cbn ( out, a, b, sel);output [3:0] out;input [3:0] a, b;input sel;// the inputs and output of the mux2 are 2 bits wideMux2hi ( .a(a[3:2]), .b(b[3:2]), .sel(sel), .out(out3:2]) );Mux2lo ( .a(a[1:0]), .b(b[1:0]), .out([out3:2]), .sel(sel) );endmodule Name of net being connected.portname(net_to_be_connected) Name of port in lower level module(period indicating a hierarchical name)10Kazi Fall 2006 EEGN 494Data ObjectsNetsNets sometimes called to wires are most common data objects to interconnect modules. The default net type is a plain wire. There are wired OR, wired AND, pullups, pulldowns etc. For synthesis use wire only!!wire a, b, c; // three 1-bit nets of type wirewire [7:0] d, e, f; // three 8-bit vectors Verilog implicitly declares nets for every port declaration. Every connection made in a module instance or primitive instance is also implicitly declared as a net, if it isn’t already declared.11Kazi Fall 2006 EEGN 494RegistersThe register (reg) data object holds its value from one procedural assignment statement to the next and holds its value from one to the next simulation cycle. It DOES NOT imply that a physical register will be synthesized.The fundamental difference between nets and registers is that the registers have to be assigned values explicitly. Once a value is assigned to a register, it is held until next procedural assignment to it.12Kazi Fall 2006 EEGN 494Registers and PortsOnly output port can be of type reg, since only way to get a value into a reg is with a procedural statement.Input ports cannot be of type reg since they do not get their value through procedural assignment. Relationship between ports and reg is shown below:Inputs:Reg or netoutside net only inside net or reg insideoutputs:Net onlyoutside inout: net only inside inout: net only outside13Kazi Fall 2006 EEGN 494NumbersNumber of bits‘radix Value‘b ‘B Binary‘d ‘D Decimal‘h ‘H Hexadecimal‘o ‘O Octal8’b100100018’d24514Kazi Fall 2006 EEGN 494Description of a flip flopmodule fflop (q, data, reset_n, clk);output q;input data, reset_n, clk;reg q;always @(posedge clk) if (reset_n == 0) // this can also be written as “if (!reset_n)” q = 1’b0; else q = data;endmodule // fflop15Kazi Fall 2006 EEGN 494Description of a flip flop with asynchronous reset_nmodule fflop_async (q, data, reset_n, clk);output q;input data, reset_n, clk;reg q;always @(posedge clk or negedge reset_n) if (!reset_n) q = 1’b0; else q = data;endmodule // fflop_async** Since the clk is not used in any conditional statement, hence implicitly the synthesis tool knows that clk is the CLOCK signal16Kazi Fall 2006 EEGN 494Arithmetic operatorsBinary: +, -, *, /, % (the modulus operator) Unary: +, - Integer division truncates


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