New version page

UVA CS 451 - Study Guide

This preview shows page 1 out of 4 pages.

View Full Document
View Full Document

End of preview. Want to read all 4 pages?

Upload your study docs or become a GradeBuddy member to access this document.

View Full Document
Unformatted text preview:

© IN-STAT MARCH 21, 2005 MICROPROCESSOR REPORTSpring 2005 IDF. At the Spring 2005 IDF, Intel had manydemos on the stage and a demo pavilion with multiple sys-tems running on multiple versions of Intel dual-core proces-sors. What a difference six months make! Intel also revealedsome surprising implementation details of its multicoremanufacturing strategy.Intel branding for the dual-core processors will drop thenumeral reference. The dual-core desktop processor, based onthe Net-Burst (Pentium 4) architecture, will be called the Pen-tium D processor. For the Pentium D, Intel will not enableHyper-Threading, so this version will perform almost identi-cally to a Xeon dual-processor SMP system today. Intel willalso offer a version of the dual-core Net-Burst processor withHyper-Threading enabled, which will be branded as a Pen-tium Processor Extreme Edition. The Pentium EE will sup-port four threads for the operating system.So far, Microsoft has decided to support the one-socket/one-operating-system/one-license pricing model forWindowsXP. That should mean that Microsoft does not careif the dual-core processor consists of one or more actual diein the package. When we get to virtualization technologies,with multiple operating system instances running, however,we will likely see Microsoft charging per instance.What Makes a Dual-Core Processor?The biggest surprise from the show was that a number offuture dual-core processors are not on a monolithic die.The first dual-core processor Intel will ship, code-namedSmithfield, will consist of two Net-Burst cores on one dieand will ship in desktop systems as the Pentium D proces-sor. The follow-on 65nm dual-core part, code-namedPresler, will have two Net-Burst cores on two separate die,but both die will be mounted in one package. This is thefirst time Intel has ventured into volume microprocessormultichip modules (MCM) since the original PentiumPro.(Intel did ship Pentium II and Pentium III processors inmodules; those modules actually consisted of a processorcore with cache SRAM chips on a daughtercard, enclosed ina plastic shell.) Although there is no user-perceivable differ-ence between the monolithic and separate die versions ofNet-Burst processors (which we’ll refrain from calling thePentium 4 architecture, as the “4” seems to be on its wayout), there are manufacturing issues. There is also the ques-tion of what constitutes a “true” dual-core processor. Doesdie-packaging integration count—or does it even matter? Intel has certainly blurred the line with Presler and theXeon server version, code-named Dempsey. If MCM packag-ing of cores counts as dual- and multicore processors, thenthe IBM Power 4 processor should have been considered aneight-core processor, because IBM shipped an MCM thatincorporated four dual-core die. (See MPR 10/06/99-02,“Power4 Focuses on Memory Bandwidth.”) Like Presler, thePower 4 doesn’t require glue logic to attach multiple coresinside the MCM package.The clear way to describe Smithfield, Presler, andDempsey would be as dual-CPU processors. All these desktopON THEROAD TO MANY-CORE µPSCores Proliferate at Intel’s Spring ’05 Developer ForumBy Kevin Krewell {3/21/05-02}In 2004, Intel publicly committed to a processor roadmap that embraced dual- and multi-core processing from servers to desktops to mobile processors. At the Fall 2004 Intel Devel-oper Forum (IDF), however, Intel had only limited demos to show. Fast-forward to March’sREPORTMICROPROCESSORTHE INSIDER’S GUIDE TO MICROPROCESSOR HARDWAREwww.MPRonline.com2and Xeon processors have two CPUs in one package, and theyenumerate to the operating systems as CPU 0 and CPU 1. Theenumeration difference between a dual-processor SMP sys-tem and a dual-CPU Pentium D is trivial.There are some disadvantages to this independent-coreapproach to multicore processors. Smithfield, Dempsey, andPresler use the Pentium 4 front-side bus to connect the cores,just as if it were a dual-processor SMP (see Figure 1). Theproblem is that Smithfield, Dempsey, and Presler processorcores generate two bus-interface loads on the processor bus.A slightly more integrated Paxville processor has the coresshare a single bus interface and have only one bus load (seeFigure 2) on the bus. The impact of the extra bus loading ofSmithfield is that the high-end Pentium Extreme Editionprocessor Intel plans to ship this year will have to slow its busto 800MHz—from the 1,066MHz of the Prescott version ofthe Pentium 4 Extreme Edition. The slower front-side bus willbe a potential bottleneck for the Extreme Edition processor,because it will be a high-clock-speed processor (likely3.2GHz) with up to four threads. Any program that is band-width sensitive may not scale well on Smithfield.The Platforms for the Dual CoreThe desktop dual-core processors will be supported by newdesktop chip sets called the Intel 945G and 955X Express chipsets. The dual-core processors will not boot in the existing915 and 925 Express chip sets. The 915/925 chip sets weredesigned for single-core processors and do not support theenumeration of multiple processors, which is the domain ofthe server chip sets today. The 945G/955X chip sets add thatcapability to the desktop platform.For the Xeon processor line, Intel will introduce a systemarchitecture called dual-independent buses (DIB). The dual-bus design (see Figure 3) is similar to the bus structure ofAMD’s original server processor, the Athlon MP. The AthlonMP was limited to dual-processor systems because the chip setcould support only enough pins for two point-to-pointprocessor connections.Beyond two-processor systems, Intel mixes the DIBwith its traditional shared-bus architecture (see Figure 4).The Paxville processor bus interface could run at 667MHzor 800MHz, because of the processor’s integrated bus inter-face, significantly faster than the 533MHz of today’s quad-processor XeonMP systems.The disadvantage of putting the chip set in the middleof the processors is that coherency traffic must pass throughthe chip set, adding latency and a potential bottleneck. Thiswas the scaling problem of the AMD Athlon MP processor.The advantage for the Intel Xeon lineup is that Intel can sig-nificantly improve bus bandwidth by reducing bus loading.The design trade-off will have different effects, dependingon the application needs. For the moment, we believe thebandwidth improvement has the performance edge over theburden of the higher-coherency-traffic latency.Yonah and


View Full Document
Loading Unlocking...
Login

Join to view Study Guide and access 3M+ class-specific study document.

or
We will never post anything without your permission.
Don't have an account?
Sign Up

Join to view Study Guide and access 3M+ class-specific study document.

or

By creating an account you agree to our Privacy Policy and Terms Of Use

Already a member?