New version page

Measurements and Analysis of Process Variability in 90nm CMOS

This preview shows page 1 out of 4 pages.

View Full Document
View Full Document

End of preview. Want to read all 4 pages?

Upload your study docs or become a GradeBuddy member to access this document.

View Full Document
Unformatted text preview:

Measurements and Analysis of Process Variability in 90nm CMOS Borivoje Nikoliü, Liang-Teck Pang Electrical Engineering and Computer Sciences, University of California, Berkeley CA 94720-1770, USA Email: {bora, ltpang}@eecs.berkeley.edu Abstract Process variability in deeply scaled CMOS has both random and systematic components, with a varying degree of spatial correlation. A test chip has been built to study the effects of circuit layout on variability of delay and power dissipation in 90nm CMOS. The delay is characterized through the spread of ring oscillator frequencies and the transistor leakage is measured by using an on-chip ADC. 1. Introduction Increased process parameter variability has been perceived as one of the major roadblocks to further technology scaling [1]. Presently, the variability is captured in the design by using simulation corners, which correspond to the values of certain process parameters that deviate by 3 standard deviations from their typical value. The variations are generally characterized as within-die (WID), die-to-die (D2D) and wafer-to-wafer (W2W) [2]. Variation of process parameters can be systematic or random, spatially or temporally correlated. Sources in the variability are in the transistors, interconnect, and in the operating environment (supply and temperature) [3]. Device parameters vary systematically because of deviations in nominal widths and lengths due to exposure and etching, variation in film thicknesses (oxide thickness, gate stack), and variation in dose of implants. Random device parameter fluctuations stem from line-edge roughness [4], Si/SiO2 and poly-Si interface roughness [5] and doping fluctuations [6]. The corner-based design approach treats all variations as being WID, with all devices on a chip being correlated. The spread of corners is increasing with technology scaling, which makes it challenging to simultaneously satisfy performance, power and parametric yield requirements. In order to better account for the variability in the design process, it is necessary to distinguish systematic shifts in parameter values from truly random ones. Simultaneously, it is important to determine the spatial correlation distance of each of these parameters [7]. While some of these relationships are generally known at the process level, they are hardly visible to the designer. The goal of this paper is to quantify systematic and random components of variability in scaled CMOS by analyzing the measured data. 2. Lithography-Induced Variations Present lithography systems employ step-and-scan method, where the stepping is used to move the wafer between major exposure fields. Within an exposure field, the mask pattern is projected through a slit of light onto a wafer [8]. In sub-wavelength lithography, the effective length of a printed gate depends on its neighborhood [9-11]. Polysilicon (polySi) lines with varying pitch will have different effective channel lengths. Isolated lines expose the resist with higher light intensity, resulting in shorter channel lengths, as illustrated in Figure 1. Dense lines also have higher depth of focus, and are more immune to defocusing of the optical system [12]. Optical proximity correction techniques in the mask processing add sublithographic assist features to control the printed critical dimensions; however, their effect is limited due to shallow depth of focus. Lens imperfections are often described through aberrations, Figure 2. Aberrations create optical path differences for each pair of rays through the imaging system. Effects such as astigmatism and spherical aberrations cause differences in exposed patterns at the level of a reticle. Coma effect [13] is a lens aberration due to lens imperfection, which may cause two identical gates surrounded with non-symmetrical features to print differently from each other [14]. Flare presents the effect of scattering and reflections of light through the projection system that cause variations in the effective CDs, Figure 3. In general, the amount of flare is dependent on the local pattern density in the mask [14]. IsolatedDenseMasksResist exposure thresholdLisoLdenseIsolatedDenseMasksResist exposure thresholdLisoLdenseResist exposure thresholdLisoLdenseFigure 1: Isolated and dense lines. 1-4244-0161-5/06/$20.00 ©2006 IEEEFigure 2: Lens imperfections. LensReflectionsSurfacescatteringResist exposure thresholdCDIntensityWith flareNo flareFigure 3: Effect of flare. Proximity effects, aberrations, and flare are usually not captured in the design process, and induce layout-dependent systematic variations in the design. 3. Test chip To evaluate the characteristics of lithography-induced variations, a test-chip in a general-purpose 90nm CMOS technology has been built, which measures ring-oscillator (RO) frequencies and transistor standby leakage currents (ILEAK) of an array of test-structures [15]. The chip contains an array of 10 u 16 tiles [16-18], occupying 1mm u 1mm area. Each tile has twelve 13-stage ring oscillators (ROs) and 12 transistors in the off-state, each with a different layout (Fig.4). The transistors consist of single poly finger, as well as a stack of three fingers. PolySi pitch is varied in the test structures to capture the effect of channel length variations. PolySi orientation, together with the properties of the two-dimensional tile array, are used to determine the effects of correlation. Non symmetrical features target measurements of the coma effect. Metal coverage is also varied in the layout to investigate the effects of anneal [19]. Figure 4. Layout variations in the test chip. Figure 5. Test chip die photo. The test chip shown in Figure 5 includes frequency dividers and an on-chip single-slope analog-to-digital converter for leakage current measurements. 4. Measurement results Measured data shows several important trends. The largest impact of layout on performance variability has the gate polySi density, which causes a systematic shift in frequency of up to 10%. D2D variation is significant resulting in a 3u std. deviation/median (3V/P) of 15% over half a wafer. Finally, WID variation for identical structures is relatively small (3V/P ~ 4%). WID spatial correlation of RO frequency shows a dependency on direction of spacing and the orientation of the gates. 4.1 Effects of layout on frequency and leakage Variations in polySi pitch spacing cause over 10% shift in frequency and a 20x shift in ILEAK (Figures 6 and


Loading Unlocking...
Login

Join to view Measurements and Analysis of Process Variability in 90nm CMOS and access 3M+ class-specific study document.

or
We will never post anything without your permission.
Don't have an account?
Sign Up

Join to view Measurements and Analysis of Process Variability in 90nm CMOS and access 3M+ class-specific study document.

or

By creating an account you agree to our Privacy Policy and Terms Of Use

Already a member?