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User Guide

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Table of ContentsAbout This GuideGuide ContentsIntroductionKey Components and FeaturesComponent LocationsFast, Asynchronous SRAMAddress Bus ConnectionsWrite Enable and Output Enable Control SignalsSRAM Data Signals, Chip Enables, and Byte EnablesFour-Digit, Seven-Segment LED DisplaySwitches and LEDsSlide SwitchesPush Button SwitchesLEDsVGA PortSignal Timing for a 60Hz, 640x480 VGA DisplayVGA Signal TimingPS/2 Mouse/Keyboard PortKeyboardMouseVoltage SupplyRS-232 Serial PortClock SourcesFPGA Configuration Modes and FunctionsFPGA Configuration Mode SettingsProgram Push Button/DONE Indicator LEDPlatform Flash Configuration StoragePlatform Flash Jumper Options (JP1)“Default” Option“Flash Read” Option“Disable” OptionJTAG Programming/Debugging PortsJTAG Header (J7)Parallel Cable IV/MultiPro Desktop Tool JTAG Header (J5)Power DistributionAC Wall AdapterVoltage RegulatorsExpansion Connectors and BoardsExpansion ConnectorsA1 Connector PinoutA2 Connector PinoutB1 Connector PinoutExpansion BoardsBoard SchematicsReference Material for Major ComponentsRSpartan-3 Starter Kit Board User GuideUG130 (v1.1) May 13, 2005Spartan-3 Starter Kit Board User Guide www.xilinx.com UG130 (v1.1) May 13, 20051-800-255-7778"Xilinx" and the Xilinx logo shown above are registered trademarks of Xilinx, Inc. Any rights not expressly granted herein are reserved. CoolRunner, RocketChips, Rocket IP, Spartan, StateBENCH, StateCAD, Virtex, XACT, XC2064, XC3090, XC4005, and XC5210 are registered trademarks of Xilinx, Inc. The shadow X shown above is a trademark of Xilinx, Inc.ACE Controller, ACE Flash, A.K.A. Speed, Alliance Series, AllianceCORE, Bencher, ChipScope, Configurable Logic Cell, CORE Generator, CoreLINX, Dual Block, EZTag, Fast CLK, Fast CONNECT, Fast FLASH, FastMap, Fast Zero Power, Foundation, Gigabit Speeds...and Beyond!, HardWire, HDL Bencher, IRL, J Drive, JBits, LCA, LogiBLOX, Logic Cell, LogiCORE, LogicProfessor, MicroBlaze, MicroVia, MultiLINX, NanoBlaze, PicoBlaze, PLUSASM, PowerGuide, PowerMaze, QPro, Real-PCI, RocketIO, SelectIO, SelectRAM, SelectRAM+, Silicon Xpresso, Smartguide, Smart-IP, SmartSearch, SMARTswitch, System ACE, Testbench In A Minute, TrueMap, UIM, VectorMaze, VersaBlock, VersaRing, Virtex-II Pro, Virtex-II EasyPath, Wave Table, WebFITTER, WebPACK, WebPOWERED, XABEL, XACT-Floorplanner, XACT-Performance, XACTstep Advanced, XACTstep Foundry, XAM, XAPP, X-BLOX +, XC designated products, XChecker, XDM, XEPLD, Xilinx Foundation Series, Xilinx XDTV, Xinfo, XSI, XtremeDSP and ZERO+ are trademarks of Xilinx, Inc. The Programmable Logic Company is a service mark of Xilinx, Inc. All other trademarks are the property of their respective owners.Xilinx, Inc. does not assume any liability arising out of the application or use of any product described or shown herein; nor does it convey any license under its patents, copyrights, or maskwork rights or any rights of others. Xilinx, Inc. reserves the right to make changes, at any time, in order to improve reliability, function or design and to supply the best product possible. Xilinx, Inc. will not assume responsibility for the use of any circuitry described herein other than circuitry entirely embodied in its products. Xilinx provides any design, code, or information shown or described herein "as is." By providing the design, code, or information as one possible implementation of a feature, application, or standard, Xilinx makes no representation that such implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of any such implementation, including but not limited to any warranties or representations that the implementation is free from claims of infringement, as well as any implied warranties of merchantability or fitness for a particular purpose. Xilinx, Inc. devices and products are protected under U.S. Patents. Other U.S. and foreign patents pending. Xilinx, Inc. does not represent that devices shown or products described herein are free from patent infringement or from any other third party right. Xilinx, Inc. assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made. Xilinx, Inc. will not assume any liability for the accuracy or correctness of any engineering or software support or assistance provided to a user.Xilinx products are not intended for use in life support appliances, devices, or systems. Use of a Xilinx product in such applications without the written consent of the appropriate Xilinx officer is prohibited.The contents of this manual are owned and copyrighted by Xilinx. Copyright 1994-2004 Xilinx, Inc. All Rights Reserved. Except as stated herein, none of the material may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of any material contained in this manual may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes.Some portions reproduced by permission from Digilent, Inc.Spartan-3 Starter Kit Board User Guide UG130 (v1.1) May 13, 2005The following table shows the revision history for this document. RVersion Revision04/26/04 1.0 Initial Xilinx release.06/07/04 1.0.1 Minor modifications for printed release.07/21/04 1.0.2 Added information on auxiliary serial port connections to Chapter 7.05/13/05 1.1 Clarified that SRAM IC10 shares eight lower data lines with A1 connector.Spartan-3 Starter Kit Board User Guide www.xilinx.com 3UG130 (v1.1) May 13, 2005 1-800-255-7778Preface: About This GuideGuide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Chapter 1: IntroductionKey Components and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Component Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Chapter 2: Fast, Asynchronous SRAMAddress Bus Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Write Enable and


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