New version page

# Chico CSCI 171 - Final Exam

Pages: 5

## This preview shows page 1-2 out of 5 pages.

View Full Document

End of preview. Want to read all 5 pages?

View Full Document
Unformatted text preview:

CSCI 171 COMPUTER ARCHITECTURE Final Exam Spring 2005**OPEN BOOK, OPEN NOTE****Do not write on the back of pages**NAMENAME:___________________________________:___________________________________ 1.(10 %) (a) Design a logic circuit which will generate a parity bit with 3 input data bits. We decided on Odd parity. Show the truth table, K-map and the minimized logic equation(if possible).(b) Implement the above logic using a PLA. Show the logic diagram of the PLA.2.(2%) Point out the difference between Big Endian and Little Endian.3.(7%)(a) The founder of “Stored program” concept is _____________________________(b) In 2’s complement number system, an overflow is detected when the following 2 bits from ALU are not same: 1)_________________ 2)__________________(c) On Fig 5.21, the function of the ALU on the upper left corner is ____________________________, the function of the ALU on the upper right corner is ___________________________,the function of the ALU on the lower right corner is either _______________________________ or __________________________________.4.(12 %) Given the block diagram of a cache(Figure 7.17 of text), answer the questions:Address228V TagIndex012253254255Data V Tag Data V Tag Data V Tag Data32224-to-1 multiplexorHit Data123891011123031 0(a) This kinds of cache organization is called as “4-way_____________________ ”(b) Total size of the cache including Valid bits, Tag fields, and Data(show your answer in number of bits)(c) When we change the above cache system to 32-way(the size of the data fields of the cache stays the same), what will be the size for the Tag field and the size of the Index field?5.(5 %) What is the main reason that the newer architectures keep adding more levels of cache memory on CPU(on-chip caches), such as L1, L2, then L3?6.(5 %) What is the main reason that we need the TLB(Translation-Lookaside Buffer)?7.(12%) Describe the types of locality and give an example for each.8.(12%) The problems with a Pipelined CPU are called “hazards”. For the hazards, complete the following table:Hazards Caused by Solved byStructuralDataControl9.(12%) Answer the following questions for the memory hierarchy.(a) Where can a block be placed?*One place only  Direct mapped*Few places  _______________________*Any place  ________________________(b) How is a block found?*Indexing only __________________*Indexing and few tag field search(comparisons) ______________________*Full search(comparisons) ______________________(c) How Writes are handled?*Write-through will write to ________________ and _________________*Write-through with Buffer will write to ___________ and ________________*Write-back will write to ____________ only and the actual write to the memory will happen when _______________________________.10.(4 points). Answer true or false for each of the following: (a) _____Most computers use direct mapped page tables. (b) _____Increasing the block size of a cache is likely to take advantage of temporal locality. (c) _____Increasing the page size tends to decrease the size of the page table. (d) _____Virtual memory typically uses a write-back strategy, rather than a write-through strategy.11.(8 points) Suppose each stage of the instruction takes the followingtimes:IF = 7 ns, ID = 5 ns, EX = 10 ns, MA = 8 ns, WB = 7 ns. What is the cycle time(in ns(nanosecond)) for a single cycle, multiple cycle, and pipelined processor? Answer: Single cycle = _____ns Multiple cycle = __ ____ ns Pipelined = ____ __ nsHow long will each processor take to implement 4 add instructions assuming no hazards occur? (Hint: Refer to Figure 5.38)Answer: Single cycle = _____ns Multiple cycle = ______ns Pipelined = ______ns12.(6 points) The average memory access time (AMT) is defined as AMT = hit_time + miss_rate x miss_penaltyFind the AMT of a 1000 MHz machine, with a miss penalty of 100 cycles, a hit time of 2 cycles, and a miss rate of 5%.Answer: ___________nanosecondsSuppose doubling the size of the cache decrease the miss rate to 3%, but causes the hit time to increases to 3 cycles and the miss penalty to increase to 110 cycles. What is the AMT of the new machine? Answer: ___________nanoseconds13.(5 points) If we divide the inner workings of a processor into two levels, (a) ISA layer and (b) computer organization layer, explain the difference between

View Full Document
Unlocking...