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A Digital Alarm System

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11/13/2007 - 1 - COMPUTER ENGINEERING PROGRAM California Polytechnic State University CPE 169 Experiment 9 – Part A A Digital Alarm System Learning Objectives 1. Finite State Machine (FSM) • To develop a State Transition Diagram description of a Finite State Machine, in preparation for implementation using VHDL behavioral modeling 2. Digital Systems Design • To understand the interaction between various modules in a digital system. • To design and implement a system-level digital circuit based on a given specification. • To practice design reuse and integration with modules designed by others. 3. Xilinx Design Methodology and VHDL • To gain more experience with VHDL structural modeling Introduction and Overview This experiment introduces a common sequential circuit in the context of digital system design: the Finite State Machine (FSM). Two common uses of the FSM are in the design of counters and system controllers. This experiment uses a FSM to control the various operating characteristics of the digital alarm system that was discussed in the previous experiments. The stated digital alarm system contains four main functional modules; three of these modules have been designed in previous experiments. The fourth module is the FSM and is the main focus of this experiment (both Parts). The various modules of the digital alarm system are integrated using VHDL structural modeling thus highlighting the code reuse approach to digital design. Finite State Machine Design Using VHDL Implementing FSMs in VHDL is most straight-forward using VHDL Behavioral Modeling. As you have probably noticed by now, any time that you are able to implement a circuit by describing its behavior (as opposed to describing the actually logic used to implement the behavior), you’ll be allowing the VHDL synthesis process to do most of the grunt-work that has traditionally been required of the circuit designer. Once you understand these techniques, you’ll be able to quickly apply them to the implementation step of any FSM problem. At this point, however, you are probably unfamiliar with the adaptations to the behavioral modeling approach that are required to implement sequential logic state machines in VHDL. Therefore, you will begin your implementation of the Digital Alarm System this week using the more familiar Structural Modeling approach for both the top-level Alarm System and the Alarm control FSM. This will permit you to integrate and test a completely working Alarm System this week; and then develop, verify, and integrate a Behavioral version of the Alarm control FSM next week that will simply replace one of your structural components in the Alarm System design.CPE 169 Experiment 9 ISE 9.1i 11/13/2007 - 2 - Integrating Modular Designs Using VHDL As an added bonus, this week you will be supplied with a completed and pre-tested VHDL structural module for the Alarm FSM that you can incorporate into your design; as if you were designing the Alarm System as part of a team of designers. Your job is then to integrate existing VHDL modules that you have already created and tested, with those supplied by your "teammate", into a complete, working, and fully tested Digital Alarm System. As is typical of such design integrations, some minor modifications may be required to the "lower-level" VHDL modules in order to achieve the desired system behaviors or design hierarchies; as well as a bit of troubleshooting / debugging. Today, you will also experience the "pleasures" of working with someone else's designs, where you will (hopefully) begin to understand and appreciate the value of well-documented VHDL code as an aid to system troubleshooting and design analysis. The complete Digital Alarm System that you will be implementing is shown in Figure 1 below. You should already have working VHDL modules for the Priority Encoder, BCD to 7-Segment Decoder, and the Comparator that you created in earlier Experiments. The VHDL modules required to implement the Alarm FSM will be provided. Figure 1: Alarm System Implemented on Nexys Board Procedure Procedure Overview: In this experiment, you’ll be integrating the various components of a digital alarm system. All but one of the components in the digital alarm system were designed and tested in previous experiments. 1) Complete a concept design for a FSM that acts as a controller for the digital alarm system. 2) Compare your Alarm FSM design concept to the operation of the FSM structural design provided. 3) Implement and test a complete Digital Alarm System using a structural (modular) design in VHDL, utilizing the existing component modules created in previous experiments and the provided structural design of the Alarm FSM. 2CPE 169 Experiment 9 ISE 9.1i 11/13/2007 - 3 - Procedure 1: Digital Alarm System FSM 1. Complete the conceptual design of a Finite State Machine to control the digital Alarm System based on the following design criteria. The black-box diagram of the FSM is shown in Figure 2. Figure 2: Black-box diagram of the digital alarm FSM. a. This FSM has three inputs (SYS_ON_L, BREAK_IN, and CLK) and two outputs (ALARM and SYS_ARMED). NOTE: The SYS_ON_L signal is active low. This means that when the signal is in the ‘0’ state, the signal is active or asserted, and the alarm system is turned on. When the signal is not asserted, the system is turned off. Therefore, in the context of the Alarm System of Figure 1, setting the correct Access Code (resulting in a '1' on the SYS_ON_L signal) will "disarm" or turn off the alarm. As shown here, active low signals are typically noted with the “_L” suffix appended onto the signal name. b. The FSM has three states: UNARMED, ARMED, and ALARM_SOUNDING. c. When the FSM is in the UNARMED state, the system is off. If the SYS_ON_L input is asserted, the FSM transitions to the ARMED state. All other input combinations keep the system in the UNARMED state. Keep in mind that turning off the alarm is only accomplished by entering the correct alarm code. If the correct alarm code is not entered, the system will "ARM" itself. d. When the FSM is in the ARMED state, the system is on and ready to detect break-ins. If the SYS_ON_L input is not asserted, the system is turned back off and goes into the UNARMED state. If the SYS_ON_L is asserted and the BREAK_IN input is asserted, the FSM transitions to the ALARM_SOUNDING state. Any other


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