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FLIP-CHIP INTEGRATED SOI-CMOS-MEMS FABRICATION TECHNOLOGY

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FLIP-CHIP INTEGRATED SOI-CMOS-MEMS FABRICATION TECHNOLOGY P. J. Gilgunn1, G. K. Fedder1,2,3 1Electrical and Computer Engineering Dept., 2The Institute for Complex Engineered Systems, and 3The Robotics Institute, Carnegie Mellon University, Pittsburgh, Pennsylvania, USA ABSTRACT A fully-dry, flip-chip fabrication technology was developed for the integration of high fill factor, silicon-on-insulator (SOI) structures and CMOS-MEMS actuators. An SOI mirror array with a fill factor of 95% and radius of curvature >1.3 m was fabricated on CMOS-MEMS electrothermal actuators using this technology. The unloaded actuators achieved an optical scan range of >92º. Following flip-chip bonding with high temperature epoxy, the structures were released using deep reactive ion etching (DRIE). Aspect ratio dependent etching (ARDE) modulated local structural silicon thickness on the CMOS-MEMS actuators and reduced notching and microtrenching on the posts of the SOI mirrors. INTRODUCTION This paper describes a process flow in which high fill factor, silicon-on-insulator (SOI) structures were integrated with CMOS-MEMS [1] actuators using flip-chip bonding. The demonstration vehicle for this SOI-CMOS-MEMS fabrication technology was an array of 1-degree-of-freedom (1-DOF), Al-coated, single crystal silicon (SCS) mirrors, bonded with high temperature epoxy to pedestals formed in CMOS-MEMS (see Fig. 1) and anchored through electrothermal actuators. Aspect ratio dependent etch modulation (ARDEM) was a key technique in the process flow. Several artifacts, such as Al undercut on the mirror and non-planarity among array elements, can be observed in Fig. 1 and are yet to be resolved. Figure 1. SEM image of a 3 x 2 array of 1-DOF, Al-coated, single crystal silicon (SCS) mirrors. The mirrors were 25 µm x 1 mm x 1 mm. The SCS posts were 500 µm tall and 120 µm across at their widest point. The pedestals and electrothermal actuators were formed in CMOS-MEMS. SCS plates under the pedestals were bulk-Si micromachined from the backside of the CMOS substrate using aspect ratio dependent etch modulation (ARDEM). The posts were bonded to the pedestals with high temperature epoxy. Dense packing and high fill factor in MEMS devices are desirable because they improve efficiency and resolution while reducing area consumption. Michalicek [2] used flip-chip bonding to fabricate electrostatically actuated, piston-motion, MUMPS mirror arrays with a 98% fill factor. Tsai [3] demonstrated electrostatically actuated scanning mirrors for optical cross-connects, with a fill factor of 96% in the SUMMiT-V technology. Packing densities of 100 cantilevers/mm2 for probe-based data storage devices were demonstrated by Despont [4] and Kim [5] using wafer-level transfer techniques and CMOS substrates. Imaging applications benefit from large optical scanning angles and high fill factors which increase scan area, light coupling and spatial resolution. However, the goals of high fill factor and large actuator stroke have not been compatible up to now. Michalicek’s piston mirrors had a 600 nm range of motion and Tsai’s scanning mirrors had an optical scanning angle of 17.6°. In contrast, the electrothermally actuated CMOS-MEMS scanning mirror reported by Jain [6] had an optical scan angle of 80°, but a fill factor of only 60%. We pioneered the SOI-CMOS-MEMS fabrication technology reported in this paper to simultaneously achieve high fill factor and large range of motion in arrayed MEMS devices. We decoupled mirror and actuator design so the properties and performance of each could be optimized independently. The material choices in this paper were made on the basis of the needs of the demonstration application and should not be considered as exclusive. Process scalability, manufacturability and robustness were concerns that we did not address experimentally, to date, and as such, no data on these subjects are presented. FABRICATION PROCESS FLOW The fabrication technology consisted of three modules: 1. post-CMOS processing (Fig. 2), 2. SOI mirror-post processing (Fig. 3), and 3. Flip-chip bonding and release processing (Fig. 4). All processing was done at chip level. Deep reactive ion etch (DRIE) processes were performed on a Surface Technology Systems (STS) Advanced Silicon Etch (ASE) inductively coupled plasma (ICP) etch tool [7]. Anisotropic silicon etching was done with a SF6/O2/C4F8, Bosch-type process [8]. A SF6 plasma was used for isotropic etching. During plasma etch processes, CMOS-MEMS and SOI die were mounted on a resist-coated, silicon carrier wafer using 150° C Revalpha thermal release tape from Nitto Denko. This material proved resistant to 7+ hours of plasma etch processing, had very low residual adhesion following thermal release and left no observable defects on the die. Post-CMOS Process Module (Fig. 2) CMOS-MEMS utilizes foundry CMOS die as a starting material (Fig. 2 (a)) [1]. The die used in this work was fabricated by Jazz Semiconductor, Newport Beach, CA in a four-metal, 0.35 µm, SiGe BiCMOS process technology. The silicon substrate, as received from the foundry, was 272 ± 5 µm. The group of steps from Fig. 2 (b) to (f) defined the final release etch mask and a SCS plate under the pedestal, which received the SOI post during flip-chip bonding. CMOS interconnect (a stack of Al and TiW, in this case) and ILD (various types of SiO2) hold residual stress that is relieved by bending after the CMOS substrate is removed. The effect of residual stress can be observed in the curling of the electrothermal actuators in Fig. 1, but the SCS plate prevented the pedestal from curling. The backside of the die was DC sputtered with 100 nm of Al at 20° C and patterned using backside-aligned, direct-write, chip-level, laser lithography on a Heidelberg Instruments DWL 66(Fig. 2 (b)). The Al was wet etched to form a hardmask (Fig. 2 (c)) to protect the substrate during the CMOS-MEMS backside release etch process. Figure 2. Post-CMOS process module schematic. Resist strip and clean steps not shown. (a) Foundry CMOS die. (b) CMOS backside Al hardmask DC sputter deposition. (c) Al hardmask patterning using backside-aligned, direct-write lithography and Al wet etch. (d) ARDEM patterning using backside-aligned, direct-write lithography. (e) Anisotropic, Bosch-type DRIE. (f) Isotropic SF6 plasma etch to remove ARDEM partitions. (g) Frontside sacrificial ILD etch using uppermost CMOS


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