ECEN 45171Lecture 4ECEN 4517/5517DC-DC converterBattery charge controllerPeak power trackerExperiment 3ECEN 45172Due datesThis week in lecture (now):Exp. 3 prelab assignment (one from every student)This week in lab:Exp. 2 scoresheetLate assignments will not be accepted. Assignments are due within five minutes of beginning of period.ECEN 45173Goals in upcoming weeksExp. 3: A multi-week experimentExp. 3 Part 1:Demonstrate dc-dc converter power stage operating open loop, driven by MSP430 PWM outputInside, with input power supply and resistive loadOutside, between PV panel and batteryDC system simulationExp. 3 Part 2:Demonstrate working sensor circuitry, interfaced to microprocessorDemonstrate peak power tracker and battery charge controller algorithms, outside with converter connected between PV panel and batteryECEN 45174Exp. 3, Part 1Demonstrate dc-dc power stage insideECEN 45175Exp. 3Minimum timetableThis week• Assemble power stage and gate driver on perf boardNext week • Get circuitry working inside lab• Take measurements outsideThird week• Perform simulations• Build sensor circuitry (Part 2)Fourth week• MPPT coding• Demonstrate operation outsideECEN 45176Layout issuesECEN 45177ECEN 45178ECEN 45179ECEN 451710ECEN 451711Converter modeling and simulationConduction modes– Continuous conduction mode (CCM)– Discontinuous conduction mode (DCM)Equivalent circuit modeling– The dc transformer model: CCM– DCM modelSimulation– Averaged switch model in CCM– Averaged switch model in DCM– A combined automatic model for PSPICE (or Simulink, optional)ECEN 451712Averaged switch modelingBasic approach (CCM)D1Q1R+V–+–CLVgGiven a switching converter operating in CCMBuck converter exampleSeparate the switching elements from the remainder of the converterDefine the terminal voltages and currents of the two-port switch networkR+V–+–CLVgD1Q1+v1–+v2–Switchnetworki1i2ECEN 451713Terminal waveforms of the switch networkRelationship between average terminal waveforms:ECEN 451714Averaged model of switch networkv1d=v2d= vgi2d=i1d= iLSov1=ddv2i2=ddi1+–+ v2(t)Ts– i1(t)TsAveraged switch network+ v1(t)Ts– i2(t)Tsd(t)d(t)v2(t)Tsd(t)d(t)i1(t)TsModeling the switch network viaaveraged dependent sourcesECEN 451715Switch Library File.subckt CCM1 1 2 3 4 5Et 1 6 value={(1-v(5))*v(3,4)/v(5)}Vdum 6 2 0Gd 4 3 value={(1-v(5))*i(Vdum)/v(5)}.ends12345CCM112345+–+–EtGdVdum6Symbol SubcircuitECEN 451716Basic CCM SEPIC ExampleFrequency ResponseIdeal SEPIC frequency response.lib switch.libVg 1 0 dc 120VL1 1 2x 800uHRL1 2x 2 1UC1 2 3 100uFL2 3 0 100uHC2 4 0 100uFRL 4 0 40Vc 5 0 dc 0.4 ac 1Rc 5 0 1MXswitch 2 0 4 3 5 CCM1.ac DEC 201 10 100kHz.PROBE.end+–12345CCM1VgL1RL1C1L2C2RL122x 3 450+–RcECEN 451717PROBE OutputSEPIC Example: Control-to-output transfer functionMagnitudePhaseECEN 451718Discontinuous Conduction ModeR+V–+–CLVgD1Q1+v1–+v2–Switchnetworki1i2• Again find average values of switch network terminal voltages and currents• Eliminate variables external to the switch network• Results on next slidesECEN 451719Input (transistor) portAveraged equivalent circuiti1(t)Ts=d12(t) Ts2Lv1(t)Tsi1(t)Ts=v1(t)TsRe(d1)Re(d1)=2Ld12Tsv1(t)Tsi1(t)TsRe(d1)+–ECEN 451720Output (diode) portAveraged equivalent circuiti2(t)Ts=d12(t) Ts2Lv1(t)Ts2v2(t)Tsi2(t)Tsv2(t)Ts=v1(t)Ts2Re(d1)= p(t)Tsp(t)+v(t)–i(t)ECEN 451721Averaged modeling of CCM and DCM switch networks+–1 : d(t)i1(t)Tsi2(t)Ts+–v2(t)Tsv1(t)TsAveraged switch modelSwitch networkCCM+v2(t)–+v1(t)–i1(t) i2(t)i2(t)Ts+–v2(t)Tsv1(t)Tsi1(t)TsRe(d1)+–DCM+v2(t)–+v1(t)–i1(t) i2(t)p(t)TsECEN 451722Spice model CCM-DCM1Combined CCM/DCM switch model•This is one of the models inside switch.lib•It automatically switches between CCM and DCM as necessaryECEN 451723PSPICE simulationExp. 3 Part 1: open loopBuck converter modelPV+–i2(t)Tsv2(t)Tsv1(t)Tsi1(t)Tsd+–+–12345CCM-DCM1PV modelBatterymodel• Use your PV model from Exp. 1• Replace buck converter switches with averaged switch model• CCM-DCM1 and other PSPICE model library elements are linked on course web
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