Modern Digital Signal ProcessorsDigital Signal Processor MarketDSPs on the Market TodayTexas InstrumentsC6000 Instruction Set ArchitectureC6000 Instruction Set ArchitectureC6000 Functional UnitsC6000 Register Accesses RestrictionsC6000 DisadvantagesC6700 Floating Point VLIW DSPC6712 vs. C6713TMS320C6200 vs. PentiumStarcoreTMS320C6200 vs. StarCore S140Slide 15Analog Devices ADSP-21161Intel/Analog Devices Blackfin DSPSlide 18LSI Logic (Dallas, TX)BenchmarkingBattery TechnologyProf. Brian L. EvansDept. of Electrical and Computer EngineeringThe University of Texas at AustinLecture 22 http://courses.utexas.edu/EE 345S Real-Time Digital Signal Processing Lab Spring 2006Modern Digital Signal Processors22 - 2Digital Signal Processor Market•Most rapidly expanding sector of semiconductor market (30% growth rate 1990-2001) •600 million cell phone subscribers worldwide (June 2001) –DSPs in more than 60% of existing cell phones –51.7 million cell phone subscribers in 1Q00 in China, the single largest market (30%) in Asia/Pacific (Dataquest) •How many digital signal processors (DSPs) are in each PC? Where are they?22 - 3DSPs on the Market Today•Berkeley Design Tech. Inc. Pocket Guide to DSPshttp://www.bdti.com/pocket/pocket.htm (see handout)Texas Inst.www.ti.com/sc/docs/dsps/dsphome.htmwww.ti.com/sc/docs/dsps/develop/3party.htm Dallas/Houston45Agere Systemswww.lucent.com/micro/dsp/ no third-party support listedAllen-town25Moto-rolawww.mot.com/SPS/DSP/ www.mot.com/SPS/DSP/developers/thirdparty.html Austin 10Analog Deviceswww.analog.com/SHARC_2154 www.analog.com/publications/press/products/3rd_party/Boston/Austin8MarketShare %Big Four Producers of DSPsDSP Information / Third-Party SupportAgere Systems was formerly the Lucent Tech. Microelectronics Group22 - 4Texas Instruments•First commercially successful DSP–Texas Instruments TMS32010 in 1982–Harvey Cragon (UT Austin) was a key part of design team•DSP processors shipped–More than 250 million in 1999 (estimated)•DSP processor revenue–$2.1 Billion of $4.4 Billion total (48% share) in 1999–$2.7 Billion of $6.1 Billion total (44% share) in 2000•Modern DSP family is TMS 320C6000–256-bit instructions: Very Long Instruction Word (VLIW)–ADSL modems, 3G basestations, video codecs22 - 5Program RAMData RAMor CacheInternal BusesControl RegsRegs (B0-B15)Regs (A0-A15).D1.M1.L1.S1.D2.M2.L2.S2CPUAddrDataExternalMemory -Sync -AsyncDMASerial PortHost PortBoot LoadTimersPwr Down C6000 Instruction Set ArchitectureSimplified ArchitectureC6200 fixed pointC6400 fixed pointC6700 floating point22 - 6C6000 Instruction Set Architecture•Address 8/16/32 bit data + 64 bit data on C67x•Load-store RISC architecture with 2 data paths–16 32-bit registers per data path (A0-15 and B0-15)–48 instructions (C62x) and 79 instructions (C67x)•Two parallel data paths with 32-bit RISC units–Data unit - 32-bit address calculations (modulo, linear) –Multiplier unit - 16 bit x 16 bit with 32-bit result–Logical unit - 40-bit (saturation) arithmetic & compares–Shifter unit - 32-bit integer ALU and 40-bit shifter–Conditionally executed based on registers A1-2 & B0-2–Work with two 16-bit halfwords packed into 32 bits22 - 7C6000 Functional Units•.M multiplication unit–16 bit x 16 bit signed/unsigned packed/unpacked•.L arithmetic logic unit–Comparisons and logic operations (and, or, and xor)–Saturation arithmetic and absolute value•.S shifter unit–Bit manipulation (set, get, shift, rotate) and branching–Addition and packed addition•.D data unit –Load/store to memory–Addition and pointer arithmetic22 - 8C6000 Register Accesses Restrictions•Each function unit has read/write ports–Data path 1 (2) units read/write A (B) registers–Data path 2 (1) can read one A (B) register per cycle•40 bit words stored in adjacent even/odd registers–Used in extended precision accumulation–One 40-bit result can be written per cycle–A 40-bit read cannot occur in same cycle as 40-bit write•Two simultaneous memory accesses cannot use registers of same register file as address pointers•No more than four reads per register per cycle22 - 9C6000 Disadvantages•No acceleration for variable length decoding–50% of computation for MPEG-2 decoding on C6x in C–Acceleration available in C6400 family•Very deep pipeline–If a branch is in the pipeline, interrupts are disabled: avoid branches by using conditional execution–No hardware protection against pipeline hazards: programmer and software tools must guard against it•No hardware looping or bit-reversed addressing•40-bit accumulation incurs performance penalty•No status register: must emulate status bits other than saturation bit (.L unit)22 - 10C6700 Floating Point VLIW DSP•32-bit floating-point VLIW DSP–Introduced in 1997–Extends C6000 instruction set for floating point arithmetic•Eight functional units: single cycle throughput–Two ALUs are fixed-point–Four ALUs support fixed-point and floating-point–Two multipliers support fixed-point and floating-point•Applications include professional audio, home entertainment, wireless base stations, medical imaging, sonar imaging, and robotics22 - 11C6712 vs. C6713•C6712•150 MHz clock,900 MFLOPS •4 kB/4kB of L1 program/data memory•64 kB of L2 cache•1200 MB/s on-chip data bus bandwidth •$13.50 each in volume•C6713•225 MHz clock,1350 MFLOPS •4 kB/4kB of L1 program/data memory•256 kB of L2 cache•1800 MB/s on-chip data bus bandwidth •$26.85 each in volumeInformation as of December 3, 200122 - 12TMS320C6200 vs. PentiumProcessor Peak MIPS BDTI 2000 marks ISR latency Power Unit Price Area Volume Pentium III 1200 2400 2690 1.14 s 4.25 W $29 5.5” x 2.5” 8.789 in3 Pentium III 1.00 s 4.85 W n/a 5.5” x 2.5” 8.789 in3 C6200 200 MHz 1600 1280 0.09 s 1.94 W $25 1.3” x 1.3” 0.118 in3 C6200 300 MHz 2400 1920 0.06 s $96 1.3” x 1.3” 0.118 in3 BDTImarks: Berkeley Design Technology Inc. DSP benchmarkresults (larger means better) http://www.bdti.com/bdtimark/results.htmhttp://www.ece.utexas.edu/~bevans/courses/ee382c/lectures/processors.html22 - 13Starcore•Startup company with two major investors–Motorola (Semiconductor Product Sector, Austin, TX)–Agere Systems (formerly Lucent Technologies Microelectronics Group, Allentown, PA) •Has developed 16-bit VLIW DSPs –SC140: 300 MHz, 1200 MMACS or 3000 RISC MIPS at 0.2mW/ MMAC at 1.5V