1Edgar GabrielCOSC 6385Computer ArchitectureInstruction Set ArchitecturesEdgar GabrielFall 2009COSC 6385 – Computer ArchitectureEdgar GabrielInstruction Set Architecture (ISA)• Definition on Wikipedia: “Part of the Computer Architecture related to programming”• Defines – set of operations, – instruction format, – hardware supported data types, – named storage, – addressing modes, – sequencing• Includes a specification of the set of opcodes (machine language) - native commands implemented by a particular CPU design2COSC 6385 – Computer ArchitectureEdgar GabrielInstruction Set Architecture (II)• ISA to be distinguished from the micro-architecture –set of processor design techniques used to implement an ISA• Example: Intel Pentium and AMD Athlon support a nearly identical ISA, but have completely different micro-architectureCOSC 6385 – Computer ArchitectureEdgar GabrielISA Specification• Relevant features for distinguishing ISA’s– Internal storage– Memory addressing– Type and size of operands– Operations– Instructions for Flow Control– Encoding of the IS3COSC 6385 – Computer ArchitectureEdgar GabrielInternal storage• Stack architecture: operands are implicitly on the top of the stack• Accumulator architecture: one operand is implicitly the accumulator• General purpose register architectures: operands have to be made available by explicit load operations– Dominant form in today’s systemsCOSC 6385 – Computer ArchitectureEdgar GabrielInternal storage (II)• Example: C= A+BStack:Push APush BAddPop CAccumulator:Load AAdd BStore CLoad-Store:Load R1,ALoad R2,BAdd R3,R1,R2Store R3,C4COSC 6385 – Computer ArchitectureEdgar GabrielInternal storage (III)• Advantage of general purpose register architectures vs. stack architectures:– Registers are fast– Easier and faster to evaluate complex expressions, e.g.(A*B)-(B*C)-(A*D)• Registers can hold temporary variables• Reduces memory traffic• A register can be named with fewer bits than main memoryCOSC 6385 – Computer ArchitectureEdgar GabrielAddressing modes• How does an ISA specify the address an object will access?Addressing mode Example instruction MeaningRegisterAdd R4,R3Regs[R4]←Regs[R4]+Regs[R3]ImmediateAdd R4,#3Regs[R4]←Regs[R4]+3Register indirectAdd R4,(R1)Regs[R4]←Regs[R4]+Mem[Regs[R1]]DisplacementAdd R4,100(R1)Regs[R4]←Regs[R4]+Mem[100+Regs[R1]]Memory indirectAdd R4, @R3Regs[R4 ] ← Regs[R4] +Mem[Mem[Regs[R3]]]5COSC 6385 – Computer ArchitectureEdgar GabrielAddressing modes (II)• Addressing modes must match– Ability of compilers to use them– Hardware characteristics• Which modes are most commonly used?– Displacement– Immediate– Register indirect• Size of address for displacement mode?– Typically 12-16 bits• Size of the immediate field?– 8-16 bitsCOSC 6385 – Computer ArchitectureEdgar GabrielInternal storage (IV)• Two major GPR architectures:– 2 or 3 operands for ALU instructions• 3 operands: 2 source, 1 result• 2 operands: 1 operand is both source and result– How many operands can be memory addresses?No. of memory addresses Max. no. of operands Architecture0 3 Register-register(load-store arch.)1 2 Register-memory2 2 Memory-memory3 3 Memory-memory6COSC 6385 – Computer ArchitectureEdgar GabrielMemory alignment (I)• Memory is typically aligned on a multiple of word boundaries• Best case: – accessing misaligned address leads to performance problems since it requires accessing multiple words• Worst case: – hardware does not allow misaligned accessCOSC 6385 – Computer ArchitectureEdgar GabrielMemory alignment (II)Width of object 0 1 2 3 4 5 6 71 byte A A A A A A A A2 bytes (half word) A A A A2 bytes (half word) M M M M4 bytes (word) A A4 bytes (word) M M4 bytes (word) M M4 bytes (word) M M8 bytes ( double word) A8 bytes ( double word) M8 bytes ( double word) M8 bytes ( double word) M8 bytes ( double word) M8 bytes ( double word) M8 bytes ( double word) M8 bytes ( double word) M7COSC 6385 – Computer ArchitectureEdgar GabrielType and size of operands (I)• How is the type of an operand designated?– Encoded in the opcode– Annotated by tags• Common operand types:– Character - 8bits– Half word - 16 bits, 2 bytes– Word - 32 bits, 4 bytes– Single precision floating point - 32 bits, 4 bytes– Double precision floating point - 64 bits, 8 bytesCOSC 6385 – Computer ArchitectureEdgar GabrielType and size of operands (II)• Encoding of characters:– ASCII– UNICODE• Encoding of integers:– Two’s complement binary numbers• Encoding of floating point numbers:– IEEE standard 754– No uniform representation of the data type long double8COSC 6385 – Computer ArchitectureEdgar GabrielOperations in the Instruction SetOperator type ExamplesArithmetic and logical Integer arithmetic: add, subtract, and, or, multiple, divideData transfer Load, store, moveControl Branch, jump, procedure call, return, trapsSystem OS call, virtual memory managementFloating point Floating point arithmetic: add, multiply, divide, compareDecimal Decimal add, multiplyString String move, string compare, string searchGraphics Pixel and vertex operations, compressionCOSC 6385 – Computer ArchitectureEdgar GabrielFlow Control instructions• Four types of different control flow changes– Conditional branches– Jumps– Procedure calls– Procedure returns• How to specify the destination address of a flow control instruction?– PC-relative: Displacement to the program counter (PC)– Register indirect: name a register containing the target address9COSC 6385 – Computer ArchitectureEdgar GabrielFlow Control instructions (II)• Register indirect jumps also required for– Case/switch statements– Virtual functions in C++– Function pointers in C– Dynamic shared libraries ( dll in Windows, .so in UNIX)• Procedure invocation: global variables could be accessed by multiple routines→ location of the variable needs to be known• Options for saving registers:– Caller saving– Callee saving→due to the possibility of separate compilation, many compilers store any global variable that may be accessed during a callCOSC 6385 – Computer ArchitectureEdgar GabrielEncoding an Instruction Set• How are instructions encoded into a binary representation– Affects size of compiled program– Affects implementation of the processor• Decision depends on range of addressing modes supported– Variable