CS 268: Lecture 10 Router Design and Packet LookupIP RouterOverviewGeneric Router ArchitectureSpeedupFunction divisionThree Router ArchitecturesOutput Queued (OQ) RoutersInput Queueing (IQ) RoutersCombined Input-Output Queueing (CIOQ) RoutersGeneric Architecture of a High Speed Router TodayBackplaneHead-of-line BlockingSolution to Avoid Head-of-line BlockingCell transferStable Marriage ProblemGale Shapely Algorithm (GSA)ExampleOQ Emulation with a Speedup of 2Slide 20A Case Study [Partridge et al ’98]Router ArchitectureSlide 23Router Architecture: Data PlaneRouter Architecture: Control PlaneData Plane Details: ChecksumData Plane Details: Slow Path ProcessingControl Plane: Backplane AllocatorThe Switch Allocator CardAllocation AlgorithmThe Switch AllocatorSummary: Design Decisions (Innovations)Slide 33Lookup ProblemSlide 35Patricia TriesLulea’s Routing Lookup Algorithm (Sigcomm’97)First Level: Bit-VectorFirst Level: PointersSlide 40Code Word and Base Indexes ArrayFirst Level: Finding Pointer GroupFirst Level: Encoding Bit-masksFirst Level: Finding Pointer IndexFirst Level: Memory RequirementsFirst Level: OptimizationsLevels 2 and 3LimitationsNotesCS 268: Lecture 10Router Design and Packet LookupScott Shenker and Ion StoicaComputer Science DivisionDepartment of Electrical Engineering and Computer SciencesUniversity of California, BerkeleyBerkeley, CA [email protected] 2IP RouterA router consists-A set of input interfaces at which packets arrive-A se of output interfaces from which packets depart Router implements two main functions-Forward packet to corresponding output interface-Manage [email protected] 3OverviewRouter ArchitectureLongest Prefix [email protected] 4Generic Router ArchitectureInput and output interfaces are connected through a backplaneA backplane can be implemented by-Shared memory •Low capacity routers (e.g., PC-based routers)-Shared bus•Medium capacity routers-Point-to-point (switched) bus • High capacity routersinput interface output interfaceInter-connectionMedium(Backplane)[email protected] 5SpeedupC – input/output link capacityRI – maximum rate at which an input interface can send data into backplaneRO – maximum rate at which an output can read data from backplaneB – maximum aggregate backplane transfer rateBack-plane speedup: B/CInput speedup: RI/COutput speedup: RO/Cinput interface output interfaceInter-connectionMedium(Backplane)[email protected] 6Function divisionInput interfaces:-Must perform packet forwarding – need to know to which output interface to send packets-May enqueue packets and perform schedulingOutput interfaces:-May enqueue packets and perform schedulinginput interface output interfaceInter-connectionMedium(Backplane)[email protected] 7Three Router ArchitecturesOutput queuedInput queued Combined Input-Output [email protected] 8Output Queued (OQ) RoutersOnly output interfaces store packetsAdvantages-Easy to design algorithms: only one congestion pointDisadvantages-Requires an output speedup of N, where N is the number of interfaces not feasibleinput interface output [email protected] 9Input Queueing (IQ) RoutersOnly input interfaces store packetsAdvantages-Easy to built •Store packets at inputs if contention at outputs -Relatively easy to design algorithms•Only one congestion point, but not output…•need to implement backpressureDisadvantages-In general, hard to achieve high utilization -However, theoretical and simulation results show that for realistic traffic an input/output speedup of 2 is enough to achieve utilizations close to 1input interface output [email protected] 10Combined Input-Output Queueing (CIOQ) RoutersBoth input and output interfaces store packetsAdvantages-Easy to built -Utilization 1 can be achieved with limited input/output speedup (<= 2)Disadvantages-Harder to design algorithms•Two congestion points•Need to design flow control-An input/output speedup of 2, a CIOQ can emulate any work-conserving OQ [G+98,SZ98] input interface output [email protected] 11Generic Architecture of a High Speed Router TodayCombined Input-Output Queued Architecture-Input/output speedup <= 2Input interface-Perform packet forwarding (and classification)Output interface-Perform packet (classification and) schedulingBackplane-Point-to-point (switched) bus; speedup N-Schedule packet transfer from input to [email protected] 12Backplane Point-to-point switch allows to simultaneously transfer a packet between any two disjoint pairs of input-output interfacesGoal: come-up with a schedule that-Meet flow QoS requirements-Maximize router throughputChallenges:-Address head-of-line blocking at inputs-Resolve input/output speedups contention-Avoid packet dropping at output if possibleNote: packets are fragmented in fix sized cells (why?) at inputs and reassembled at outputs -In Partridge et al, a cell is 64 B (what are the trade-offs?)[email protected] 13Head-of-line BlockingThe cell at the head of an input queue cannot be transferred, thus blocking the following cells Cannot betransferred because output buffer fullCannot be transferred because is blocked by red cell Output 1Output 2Output 3Input 1Input 2Input [email protected] 14Solution to Avoid Head-of-line BlockingMaintain at each input N virtual queues, i.e., one per output Output 1Output 2Output 3Input 1Input 2Input [email protected] 15Cell transfer Schedule: ideally, find the maximum number of input-output pairs such that:-Resolve input/output contentions-Avoid packet drops at outputs-Packets meet their time constraints (e.g., deadlines), if anyExample:-Use stable matching-Try to emulate an OQ [email protected] 16Stable Marriage ProblemConsider N women and N menEach woman/man ranks each man/woman in the order of their preferencesStable matching, a matching with no blocking pairsBlocking pair; let p(i) denote the pair of i-There are matched pairs (k, p(k)) and (j, p(j)) such that k prefers p(j) to p(k), and p(j) prefers k to [email protected] 17Gale Shapely Algorithm (GSA)As long as there is a free man m-m proposes to highest ranked women w in his list he hasn’t proposed yet-If w is free, m an w are
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