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Advanced Programming and Execution Models



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Advanced Programming and Execution Models for Future Multi Core Systems Hans P Zima Jet Propulsion Laboratory California Institute of Technology Pasadena CA and Institute of Computational Science University of Vienna Austria High Performance Embedded Computing HPEC Workshop MIT Lincoln Laboratory 18 20 September 2007 Contents 1 Introduction 2 Towards High Level Programming Models for Parallelism High Level 3 Outline of a Generic Introspection Framework 4 Concluding Remarks Multicore An Emerging Technology The Problem CMOS manufacturing technology approaches physical limits 0 power wall memory wall ILP wall 0 Moore s Law still in force number of transistors on a chip increasing Solution Multicore technology 0 improvements by multiple cores on a chip rather than higher frequency 0 on chip resource sharing provides cost and performance benefits Multicore systems have been produced since 2000 0 IBM Power 4 Sun Niagara AMD Opteron Intel Xeon 0 Quadcore systems by AMD Intel recently introduced 0 IBM Sony Toshiba Cell Broadband Engine Power Processor PPE and 8 Synergistic PEs SPEs peak performance 230 GF 1 TF expected by 2010 Future Multicore Architectures From 10s to 100s of Processors on a Chip Tile64 Tilera Tilera Corporation 2007 0 64 identical cores arranged in an 8X8 grid 0 iMesh on chip network 27 Tb sec bandwidth 0 170 300mW per core 600 MHz 1 GHz 0 192 GOPS 32 bit Kilocore 1025 Rapport Inc and IBM 2008 0 Power PC and1024 8 bit processing elements 0 125 MHz per processing element 0 32X32 stripe configuration 0 stripes dedicated to different tasks 512 core SING chip Alchip Alchip Technologies 2008 512 core 0 for GRAPE DR a Japanese supercomputer project expected to deliver 2PFLOPS in 2008 80 core 1 TF research chip from Intel 2011 80 core HPC Massive Parallelism Dominates the Path to Peta Scale Machines IBM BlueGene L 131 072 Processors 280 TF Linpack Number 1 on TOP 500 List since 2006 System 64 racks 64x32x32 131 072 processors Rack 32 Node boards 8x8x16 2048



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