MIPS32® Architecture For Programmers Volume I: Introduction to the MIPS32® ArchitectureTable of ContentsList of FiguresList of TablesAbout This Book1.1 Typographical Conventions1.1.1 Italic Text1.1.2 Bold Text1.1.3 Courier Text1.2 UNPREDICTABLE and UNDEFINED1.2.1 UNPREDICTABLE1.2.2 UNDEFINED1.2.3 UNSTABLE1.3 Special Symbols in Pseudocode Notation1.4 For More InformationThe MIPS Architecture: An Introduction2.1 MIPS32 and MIPS64 Overview2.1.1 Historical Perspective2.1.2 Architectural Evolution2.1.2.1 Release 2 of the MIPS32 Architecture2.1.3 Architectural Changes Relative to the MIPS I through MIPS V Architectures2.2 Compliance and Subsetting2.3 Components of the MIPS Architecture2.3.1 MIPS Instruction Set Architecture (ISA)2.3.2 MIPS Privileged Resource Architecture (PRA)2.3.3 MIPS Application Specific Extensions (ASEs)2.3.4 MIPS User Defined Instructions (UDIs)2.4 Architecture Versus Implementation2.5 Relationship between the MIPS32 and MIPS64 Architectures2.6 Instructions, Sorted by ISA2.6.1 List of MIPS32 Instructions2.6.2 List of MIPS64 Instructions2.7 Pipeline Architecture2.7.1 Pipeline Stages and Execution Rates2.7.2 Parallel Pipeline2.7.3 Superpipeline2.7.4 Superscalar Pipeline2.8 Load/Store Architecture2.9 Programming Model2.9.1 CPU Data Formats2.9.2 FPU Data Formats2.9.3 Coprocessors (CP0-CP3)2.9.4 CPU Registers2.9.4.1 CPU General-Purpose Registers2.9.4.2 CPU Special-Purpose Registers2.9.5 FPU Registers2.9.6 Byte Ordering and Endianness2.9.6.1 Big-Endian Order2.9.6.2 Little-Endian Order2.9.6.3 MIPS Bit Endianness2.9.6.4 Addressing Alignment Constraints2.9.6.5 Unaligned Loads and Stores2.9.7 Memory Access Types2.9.7.1 Uncached Memory Access2.9.7.2 Cached Memory Access2.9.8 Implementation-Specific Access Types2.9.9 Cache Coherence Algorithms and Access Types2.9.10 Mixing Access TypesApplication Specific Extensions3.1 Description of ASEs3.2 List of Application Specific Instructions3.2.1 The MIPS16e™ Application Specific Extension to the MIPS32Architecture3.2.2 The MDMX™ Application Specific Extension to the MIPS64 Architecture3.2.3 The MIPS-3D® Application Specific Extension to the MIPS32 Architecture3.2.4 The SmartMIPS® Application Specific Extension to the MIPS32 Architecture3.2.5 The MIPS® DSP Application Specific Extension to the MIPS32 Architecture3.2.6 The MIPS® MT Application Specific Extension to the MIPS32 ArchitectureOverview of the CPU Instruction Set4.1 CPU Instructions, Grouped By Function4.1.1 CPU Load and Store Instructions4.1.1.1 Types of Loads and Stores4.1.1.2 Load and Store Access Types4.1.1.3 List of CPU Load and Store Instructions4.1.1.4 Loads and Stores Used for Atomic Updates4.1.1.5 Coprocessor Loads and Stores4.1.2 Computational Instructions4.1.2.1 ALU Immediate and Three-Operand Instructions4.1.2.2 ALU Two-Operand Instructions4.1.2.3 Shift Instructions4.1.2.4 Multiply and Divide Instructions4.1.3 Jump and Branch Instructions4.1.3.1 Types of Jump and Branch Instructions Defined by the ISA4.1.3.2 Branch Delays and the Branch Delay Slot4.1.3.3 Branch and Branch Likely4.1.3.4 List of Jump and Branch Instructions4.1.4 Miscellaneous Instructions4.1.4.1 Instruction Serialization (SYNC and SYNCI)4.1.4.2 Exception Instructions4.1.4.3 Conditional Move Instructions4.1.4.4 Prefetch Instructions4.1.4.5 NOP Instructions4.1.5 Coprocessor Instructions4.1.5.1 What Coprocessors Do4.1.5.2 System Control Coprocessor 0 (CP0)4.1.5.3 Floating Point Coprocessor 1 (CP1)4.1.5.4 Coprocessor Load and Store Instructions4.2 CPU Instruction FormatsOverview of the FPU Instruction Set5.1 Binary Compatibility5.2 Enabling the Floating Point Coprocessor5.3 IEEE Standard 7545.4 FPU Data Types5.4.1 Floating Point Formats5.4.1.1 Normalized and Denormalized Numbers5.4.1.2 Reserved Operand Values-Infinity and NaN5.4.1.3 Infinity and Beyond5.4.1.4 Signalling Non-Number (SNaN)5.4.1.5 Quiet Non-Number (QNaN)5.4.1.6 Paired Single Exceptions5.4.1.7 Paired Single Condition Codes5.4.2 Fixed Point Formats5.5 Floating Point Register Types5.5.1 FPU Register Models5.5.2 Binary Data Transfers (32-Bit and 64-Bit)5.5.3 FPRs and Formatted Operand Layout5.6 Floating Point Control Registers (FCRs)5.6.1 Floating Point Implementation Register (FIR, CP1 Control Register 0)5.6.2 Floating Point Control and Status Register (FCSR, CP1 Control Register 31)5.6.3 Floating Point Condition Codes Register (FCCR, CP1 Control Register 25)5.6.4 Floating Point Exceptions Register (FEXR, CP1 Control Register 26)5.6.5 Floating Point Enables Register (FENR, CP1 Control Register 28)5.7 Formats of Values Used in FP Registers5.8 FPU Exceptions5.8.0.1 Precise Exception Mode5.8.1 Exception Conditions5.8.1.1 Invalid Operation Exception5.8.1.2 Division By Zero Exception5.8.1.3 Underflow Exception5.8.1.4 Overflow Exception5.8.1.5 Inexact Exception5.8.1.6 Unimplemented Operation Exception5.9 FPU Instructions5.9.1 Data Transfer Instructions5.9.1.1 Data Alignment in Loads, Stores, and Moves5.9.1.2 Addressing Used in Data Transfer Instructions5.9.2 Arithmetic Instructions5.9.3 Conversion Instructions5.9.4 Formatted Operand-Value Move Instructions5.9.5 Conditional Branch Instructions5.9.6 Miscellaneous Instructions5.10 Valid Operands for FPU Instructions5.11 FPU Instruction Formats5.11.1 Implementation NoteInstruction Bit EncodingsA.1 Instruction Encodings and Instruction ClassesA.2 Instruction Bit Encoding TablesA.3 Floating Point Unit Instruction Format EncodingsRevision HistoryDocument Number: MD00082Revision 2.50July 1, 2005MIPS Technologies, Inc.1225 Charleston RoadMountain View, CA 94043-1353Copyright © 2001-2003,2005 MIPS Technologies Inc. All rights reserved.MIPS32® Architecture For ProgrammersVolume I: Introduction to the MIPS32®ArchitectureCopyright © 2001-2003,2005 MIPS Technologies, Inc. All rights reserved.Unpublished rights (if any) reserved under the copyright laws of the United States of America and other countries.This document contains information that is proprietary to MIPS Technologies, Inc. ("MIPS Technologies"). Any copying,reproducing, modifying or use of this information (in whole or in part) that is not expressly permitted in writing by MIPS Technologiesor an authorized third party is strictly prohibited. At a minimum, this information is protected under unfair competition and copyrightlaws. Violations thereof may result in criminal penalties and fines.Any document provided in source format (i.e., in a modifiable form such as in FrameMaker or Microsoft Word format) is subject touse and