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Systems Design and Programming Micro. Arch. I CMPE 3101 (Feb. 2, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Basic ArchitectureOutline:• Internal programmer visible architecture, e.g. registers• Real Mode Addressing:Real Mode Memory: 00000H-FFFFFH (the first 1MB of main memory).• Protected Mode Addressing:All of memory (applicable to 80286 and later processors).Programmer invisible registers to control and operate the protected memorysystem.• 80x86 Memory Paging.Systems Design and Programming Micro. Arch. I CMPE 3102 (Feb. 2, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Programmer Visible ArchitectureProgrammer visible registers:EAXEBXECXEDXESPEBPEDIESIAHALBHBLCHCLDHDLAXBXCXDXSPBPDISIAccumulatorBase IndexCountDataStack PointerBase PointerDestination IndexSource IndexEIPEFLAGSIPFLAGSInstruction PointerFlagsCodeDataExtraStackCSDSESSSFSGS80386-Pentium III only16-bitregisters32-bitextensionsAH ALAX8-bit16-bitnamesSystems Design and Programming Micro. Arch. I CMPE 3103 (Feb. 2, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Programmer Visible ArchitectureGeneral Purpose Registers: The main functions are listed.• EAX: Accumulator: Referenced as EAX, AX, AL or AH.Used for mult, div, etc.Used to hold an offset.• EBX: Base Index:Used to hold the offset of a data pointer.• ECX: Count:Used to hold the count for some instructions, REP and LOOP.Used to hold the offset of a data pointer.• EDX: Data:Used to hold a portion of the result for mult, of the operand for div.Used to hold the offset of a data pointer.• EBP: Base Pointer:Holds the base pointer for memory data transfers.• EDI: Destination Index:Holds the base destination pointer for string instructions.• ESI: Source Index:Holds the base source pointer for string instructions.Systems Design and Programming Micro. Arch. I CMPE 3104 (Feb. 2, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Programmer Visible ArchitectureSpecial Purpose Registers:• EIP: Instruction Pointer:Points to the next instruction in a code segment.16-bits (IP) in real mode and 32-bits in protected mode.• ESP: Stack Pointer:Used by the stack, call and return instructions.• EFLAGS:Store the state of various conditions in the microprocessor.Systems Design and Programming Micro. Arch. I CMPE 3105 (Feb. 2, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Programmer Visible ArchitectureSpecial Purpose Registers:EFLAGS Register: The rightmost 5 flag bits and overflow change after many of the arithmetic andlogic instructions execute. Data transfer and control instructions never changethe flags.• C (Carry):Holds the carry out after addition or the borrow after subtraction.Also indicates error conditions.• P (Parity):0 for odd number of bits and 1 for even.Obsolete feature of the 80x86.• A (Auxiliary Carry):Highly specialized flag used by DAA and DAS instructions after BCD addi-tion or subtraction.C02P4A6Z7S8T9I10D11OIOP012IOP11314NT16171819202131RFVMACVIFVIPIDSystems Design and Programming Micro. Arch. I CMPE 3106 (Feb. 2, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Programmer Visible ArchitectureSpecial Purpose Registers:• EFLAGS (cont).• Z (Zero):1 if the result of an arithmetic or logic instruction is 0.• S (Sign):1 if the sign of the result of an arith. or logic instruction is negative.• T (Trap):Trap enable. The microprocessor interrupts the flow of instructions on con-ditions indicated by the debug and control registers.• I (Interrupt):Controls the operation of the INTR (Interrupt request) pin. If 1, interruptsare enabled. Set by STI and CLI instructions.• D (Direction):Selects with increment or decrement mode for the DI and/or SI registers dur-ing string instructions. If 1, registers are automatically decremented. Set bySTD and CLD instructions.• O (Overflow):Set for addition and subtraction instructions.Systems Design and Programming Micro. Arch. I CMPE 3107 (Feb. 2, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Programmer Visible ArchitectureSpecial Purpose Registers:• EFLAGS (cont).80286 and up:• IOPL (I/O privilege level):It holds the privilege level at which your code must be running in order toexecute any I/O-related instructions. 00 is the highest.• NT (Nested Task):Set when one system task has invoked another through a CALL instructionin protected mode.80386 and up:• RF (Resume):Used with debugging to selectively mask some exceptions.• VM (Virtual Mode):When 0, the CPU can operate in Protected mode, 286 Emulation mode orReal mode. When set, the CPU is converted to a high speed 8086. This bithas enormous impact.Systems Design and Programming Micro. Arch. I CMPE 3108 (Feb. 2, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Programmer Visible ArchitectureSpecial Purpose Registers:• EFLAGS (cont).80486SX and up:• AC (Alignment Check):Specialized instruction for the 80486SX.Pentium and up:• VIF (Virtual Interrupt Flag):Copy of the interrupt flag bit.• VIP (Virtual Interrupt Pending):Provides information about a virtual mode interrupt.• ID (Identification):Supports the CPUID instruction, which provides version number and manu-facturer information about the microprocessor.Systems Design and Programming Micro. Arch. I CMPE 3109 (Feb. 2, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Programmer Visible ArchitectureSegment Registers:• CS (Code Segment):In real mode, this specifies the start of a 64KB memory segment.In protected mode, it selects a descriptor.The code segment is limited to 64KB in the 8086-80286 and 4 GB in the 386and above.• DS (Data Segment):Similar to the CS except this segment holds data.• ES (Extra Segment):Data segment used by some string instructions to hold destination data.• SS (Stack Segment):Similar to the CS except this segment holds the stack.ESP and EBP hold offsets into this segment.• FS and GS: 80386 and up.Allows two additional memory segments to be defined.Systems Design and Programming Micro. Arch. I CMPE 31010 (Feb. 2, 2002)UMBCU M B CUNIVERSITY OF MARYLAND BALTIMORE COUNTY1 9 6 6Real Mode Memory AddressingOnly mode available to the 8086 and 8088.Allow the processor to address only the first 1MB of memory.DOS requires real mode.Segments and Offsets:Effective address = Segment address + an offset.FFFFF00000100001 MB80881 0 0 0Segment register1F000OffsetF


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UNM CMPE 310 - Basic Architecture

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