Brown CS 295 - Intel Assembly
School name Brown University
Course Cs 295-
Pages 48

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Scott M. LewandowskiCS295-2: Advanced Topics in DebuggingSeptember 21, 1998Intel x86 Assembly & Debugging SupportScott M. Lewandowski CS295-2: Advanced Topics in Debugging September 21, 1998Slide 2Assembler Syntaxn Everything looks like this:label: instruction dest,srcinstruction labeln Comments:comment $This is a commentcommend $; Single line commentn Immediate values:123, 0123,0x123, 123h, ‘m’, ‘\n’Intel x86 Assembly & Debugging SupportScott M. Lewandowski CS295-2: Advanced Topics in Debugging September 21, 1998Slide 3Memory Organizationn 4 Gigabytes of addressable memoryn Support for segmentation and pagingn “Flat” memory model is a special case ofsegmentationIntel x86 Assembly & Debugging SupportScott M. Lewandowski CS295-2: Advanced Topics in Debugging September 21, 1998Slide 4Data Typesn Bytes, words, doublewords, quadwordsn Little-endiann Basically no alignment restrictionsn Recognized typesl Integerl Ordinall BCD integer, packed BCD integerl Near pointer, far pointerl Bit field, bit string, byte stringl Floating point typesIntel x86 Assembly & Debugging SupportScott M. Lewandowski CS295-2: Advanced Topics in Debugging September 21, 1998Slide 5Registersn Sixteen registers for application programmersl 8 general (32-bit)uEEX, EBX, ECX, EDX, EBP, ESP, ESI, EDIl 6 segment (16 bit): determine accessible codel 2 status and control: state of processoruAll condition codes kept in EFLAG (32-bit)uDF (of EFLAGS): controls string instructionsn EIPl Offset in code segmentl Not directly accessible to programmerIntel x86 Assembly & Debugging SupportScott M. Lewandowski CS295-2: Advanced Topics in Debugging September 21, 1998Slide 6Non-32-Bit Registersn Aliases provided for registersl EBP, ESI, EDI, and ESPuCan access bits 0-15 as BP, SI, DI, and SPl EAX, EBX, ECX, and EDXuCan access bits 0-15 as AX, BX, CX, and DXuCan access bits 0-7 as AL, BL, CL, and DLuCan access bits 8-15 as AH, BH, CH, DHn These are carryovers from 80286, but are useful31 0AH AL781516EAX AXIntel x86 Assembly & Debugging SupportScott M. Lewandowski CS295-2: Advanced Topics in Debugging September 21, 1998Slide 7Stack Implementationn Supported by three registersl Stack segment (SS): current stackl Stack pointer (ESP): offset to top of stackl Stack frame-base pointer (EBP)uAccess data structures passed on the stackuStandard to copy ESP to EBP on procedure entryIntel x86 Assembly & Debugging SupportScott M. Lewandowski CS295-2: Advanced Topics in Debugging September 21, 1998Slide 8Stack LayoutStack Segment31 0SubroutinePassedVariablesTop of StackBottom of StackEBPESPIntel x86 Assembly & Debugging SupportScott M. Lewandowski CS295-2: Advanced Topics in Debugging September 21, 1998Slide 9Instruction Formatn Prefixesl Segment overridel Address and operand sizel Repeatl Lockn Opcode and implicit operand(s)n Register specifiern Addressing mode specifiern Scale, index, base (SIB) typen Displacementn Immediate operand (data)Intel x86 Assembly & Debugging SupportScott M. Lewandowski CS295-2: Advanced Topics in Debugging September 21, 1998Slide 10Instruction Examplesn XCHG EAX, EBXn ADD [EBP+8][ESI*4], 17n MOV EAX, SS:[42H]Intel x86 Assembly & Debugging SupportScott M. Lewandowski CS295-2: Advanced Topics in Debugging September 21, 1998Slide 11Data Addressing Modesn MOV EAX, 123h Immediaten MOV EAX, NUMBER1 Directl NUMBER1 is a variable (address)n MOV EAX,EBX Registern MOV EAX,[EBX] Register Indirectn MOV EAX,[EBX+8] Register Relativel Operand is at EBX+8 (can also write 8[EBX])n MOV [EAX+ESI],EBX Base Indexedl Base and index registers determine the addressn MOV EAX,[EBX+EDI+2] Base Index Relativel Base and index register plus immediate offset are addedIntel x86 Assembly & Debugging SupportScott M. Lewandowski CS295-2: Advanced Topics in Debugging September 21, 1998Slide 12Instruction Addressing Modesn Offsets calculated from start of next instructionn JMP LABEL1 Directl Processor adds offset LABEL1 to EIPn JMP EBX Register Indirectn JMP [EBX] Memory Indirectn JMP FAR LABEL Direct Intersegmentl Allows control to pass to another segmentl Segment and offset addresses put in commandn JMP DWORD PTR [EBX] Indirect Intersegmentl Load words pointer to by EBX into ECS and EIPl DWORD PTR indicates the double-word at [EBX] should be usedIntel x86 Assembly & Debugging SupportScott M. Lewandowski CS295-2: Advanced Topics in Debugging September 21, 1998Slide 13Segmentation: “What” & “Why”n What is a segment?l Provides an independent memory spacesl Holds code, data, or stackl Has address space up to 4GBl Visible to programmern Why segmentation?l Provide separate memory spacesl Segments can be individually controlledl To access large amounts of memoryuUp to 16,383 segments of size up to 4GB = 64TBIntel x86 Assembly & Debugging SupportScott M. Lewandowski CS295-2: Advanced Topics in Debugging September 21, 1998Slide 14Segmented AddressingOperandSegment SelectorOffset Within Segment015031Intel x86 Assembly & Debugging SupportScott M. Lewandowski CS295-2: Advanced Topics in Debugging September 21, 1998Slide 15Segment Registersn Determine the segments a program can accessn Total of sixuCS: points to code segment– CALL and JMP instructionsuDS: points to main data area– Data instructions (MOV, etc.)uSS: stack segment (often same as data segment)– PUSH and POP instructionsuES, FS, GS: special informationn Can specify which segment an instruction usesl Example: MOV EAX, CS:[0]Intel x86 Assembly & Debugging SupportScott M. Lewandowski CS295-2: Advanced Topics in Debugging September 21, 1998Slide 16Segmentation: Historical Noten We are discussing 80386 segmentationn 80286 and earlier limited segment size to 64KBl Compatibility with the 8080 (64KB address space)l Allowed 16 bit addressing to continue whileproviding access to more memoryIntel x86 Assembly & Debugging SupportScott M. Lewandowski CS295-2: Advanced Topics in Debugging September 21, 1998Slide 17How Segmentation Worksn Segment descriptor: address and sizen Physical address = offset + base addressn Pointer into a segmentl Segment selector: 16 bits to identify a segmentl Offset: 32 bit address with a segmentn CR0 register toggles between direct mapping tophysical memory and using pagingIntel x86 Assembly & Debugging SupportScott M. Lewandowski CS295-2: Advanced Topics in Debugging September 21, 1998Slide 18Do We Still Need Segmenting?n Not required for memory access purposesn Can be used to implement memory managementn Most operating systems use a flat-memory modell


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Brown CS 295 - Intel Assembly

Course: Cs 295-
Pages: 48
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