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Yield and Redundancy Marc Riedel Caltech Iris Bahar Brown U Etienne Jacobs Magma Diana Marculescu CMU Phillip Stanley Marbell CMU Eric Rotenberg NCSU Problem The goal Achieving reliable computing systems from devices with high defect rates Reliability Aware Synthesis Redundancy driven synthesis what to replicate Given a technique for improving fault tolerance how do we judge the efficacy of it in terms of a combination of performance reliability power consumption etc Observable nodes Devices with high fanout Instead of redundancy removal Redundancy addition for increased reliability Fault Model Where to handle it Level of abstraction What to handle Types of faults 2 Related Research Logic Level RT level O1 O2 Still open Architectural level Von Neumann 56 Assumptions Pippenger 94 Purely theoretical not automated m m O3 Slipstream processors NCSU Diva UMich System level CMP based mainframes do use redundancy for increased faulttolerance 3 What is most susceptible to failures Failures at inputs versus outputs Need a measure of Inputs potentially propagates throughout the circuit But may be masked by other signals At primary output must be masked for correct I O behavior How susceptible a gate is to fail Or which devices when failed will be most critical to the correct functioning of the system Here synthesis can play a major role 4 Possible Approaches What works A lot of redundancy Biologically inspired approaches Models of computation and relation to the ability synthesize fault free systems Can models such as how the brain works and work on neural nets be used in contrast to traditional logic Do we need to have emulate another type of logic e g threshold logic For analysis borrow extend ideas from Information Theory 5 Open Questions No guarantee of complete reliability but rather a specifiable probability of correct functioning Reduce cost of testing by testing only what really matters What parts of the circuit should be made redundant Check only the checker Identify

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