San Jose State UniversityDr. Tri Caohuu, ENG 375EE 270 HONOR CODEEE 270 Fall 2009 San Jose State UniversityDepartment of Electrical EngineeringCourse Title: Advanced Logic DesignMeeting: TTh 18:00 - 19:15, SCI258Lab Open Lab, E389/E291Instructor:Dr. Tri Caohuu, ENG 375Email: [email protected]: (408) 924 3951Course Outline: This course presents principles and techniques in logic design: design andanalysis of combinational logic circuit; flip-flop properties, sequential circuit analysis andsynthesis, algorithmic state machines; asynchronous circuit design and analysis; anddesign for testability.The students are required to do exercises and a design project in the openlaboratory using HDL-based methodology. The course is intended for senior students andbeginning graduate student in the digital design concentration.Text: 1. Digital Logic Circuit Analysis and Design, V. P. Nelson, H. T. Nagle, B. D. Carroll, J. D. Irwin, H Prentice Hall 19954. Asynchronous Circuit Design, Chris J. Myers, Prentice Hall 2001Ref. Text:1. Digital Principles and Design, Donald Givone McGrawHill 20032. Contemporary Logic Design, Randy h. Katz and Gaetano Borriello, Prentice Hall 2005Grading policy:Midterm 1 15%Midterm 2 20%Projects 25%Final Exam 40%Office Hours: TTh: 14:30 - 16:30 F: 11:00 to 12:00Open Laboratory: E 289, E291/Unix-based and E 389/PC-basedPage 1EE 270 Fall 2009COURSE OUTLINEI. Introduction [Week 1 and 2] Review of switching algebra Analysis and synthesis of combinational logic Synchronous vs asynchronous circuits HDL tools II. Simplification of switching functions [Week 3 and 4] Karnaugh Maps Quine-McCluskey method Espresso AlgorithmIII. Synchronous circuit design [Week 5, 6, 7, 8] Sequential devices Analysis and synthesis of synchronous sequential circuits Simplification and Optimization of Sequential Circuit IV. Asynchronous sequential circuits [Week 10, 11, 12,13] Huffman Circuit Muller Circuit Timed Circuit Petri-net and Graph-based Methods Transformation Methods Asynchronous data path (pipelines) Verification V. Introduction to design for testability [Week 14,15]Page 2EE 270 Fall 2009 Fault models Combinational circuit testing Sequential logic circuit  DFT BIST VI. Design ProjectNote: Week 9 is for review and midtermCourse Learning Objectives:1. The ability to understand fundamental concepts of synchronous circuit design2. The ability to perform simplification of switching functions3. The ability to analyze and synthesize synchronous circuits4. The ability to understand the classification of asynchronous circuit. 5. The ability to analyze and synthesis fundamental asynchronous circuit design6. The ability to use HDL for modeling and verification purposes7. The ability design and test certain class of synchronous and asynchronous circuits 8. The ability to understand fundamental concepts and practices of DFTPage 3EE 270 Fall 2009University, College, or Department Policy Informationa) Academic integrity statement (from Office of Judicial Affairs):“Your own commitment to learning, as evidenced by your enrollment at San José State University and the University’s Academic Integrity Policy requires you to be honest in all your academic course work. Facultyare required to report all infractions to the Office of Judicial Affairs. The policy on academic integrity can be found at http://www2.sjsu.edu/senate/S04-12.pdfb) Campus policy in compliance with the Americans with Disabilities Act:“If you need course adaptations or accommodations because of a disability, or if you need special arrangements in case the building must be evacuated, please make an appointment with me as soon as possible, or see me during office hours. Presidential Directive 97-03 requires that students with disabilities register with DRC to establish a record of their disability.”c) Cell Phones: Students will turn their cell phones off or put them on vibrate mode while in class. They will not answer their phones in class. Students whose phones disrupt the course and do not stop when requested by the instructor will be referred to the Judicial Affairs Officer of the University.d) Academic Honesty: Faculty will make every reasonable effort to foster honest academic conduct in their courses. They will secure examinations and their answers so that students cannot have prior access to them and proctor examinations to prevent students from copying or exchanging information. They will be on the alert for plagiarism. Faculty will provide additional information, ideally on the green sheet, about other unacceptable procedures in class work and examinations. Students who are caught cheating will be reported to the Judicial Affairs Officer of the University, as prescribed by Academic Senate Policy S04-12. EE Department Honor CodeThe Electrical Engineering Department will enforce the following Honor Code that must be read and accepted by all students.“I have read the Honor Code and agree with its provisions. My continued enrollment in this course constitutes full acceptance of this code. I will NOT:- Take an exam in place of someone else, or have someone take an exam in my place- Give information or receive information from another person during an exam- Use more reference material during an exam than is allowed by the instructor- Obtain a copy of an exam prior to the time it is given- Alter an exam after it has been graded and then return it to the instructor for re-grading- Leave the exam room without returning the exam to the instructor.”Measures Dealing with Occurrences of Cheating- Department policy mandates that the student or students involved in cheating will receive an “F” on that evaluation instrument (paper, exam, project, homework, etc.) and will be reported to the Department and the University.- A student’s second offense in any course will result in a Department recommendation of suspension from the University.Page 4EE 270 Fall 2009APPENDIX:• “In addition to my specifically posted office hours, I am available on Fridays by arrangement.• “You are responsible for understanding the policies and procedures about add/drops, academic renewal, withdrawal, etc. found at http://www2.sjsu.edu/senate/S04-12.pdf• Expectations