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TAMU CSCE 614 - lecture 01

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CPSC 614:Graduate Computer Architecture Prof. Lawrence Rauchwerger IntroductionOutlineWhy take CPSC 614?Example Hot Developments ca. 2002Forces on Computer ArchitectureAmazing Underlying Technology ChangeA take on Moore’s LawTechnology TrendsPerformance TrendsMeasurement and EvaluationWhat is “Computer Architecture”?Coping with CPSC 614Review of Fundamental ConceptsThe Instruction Set: a Critical InterfaceInstruction Set ArchitectureOrganizationReview: MIPS R3000 (core)Review: Basic ISA ClassesInstruction FormatsMIPS Addressing Modes & FormatsCray-1: the original RISCVAX-11: the canonical CISCReview: Load/Store ArchitecturesMIPS R3000 ISA (Summary)Levels of RepresentationExecution CycleWhat’s a Clock Cycle?Fast, Pipelined Instruction InterpretationSequential LaundryPipelined Laundry Start work ASAPPipelining LessonsInstruction PipeliningExample: MIPS (Note register location)5 Steps of MIPS Datapath Figure 3.1, Page 130, CA:AQA 2e5 Steps of MIPS Datapath Figure 3.4, Page 134 , CA:AQA 2eVisualizing Pipelining Figure 3.3, Page 133 , CA:AQA 2eIts Not That Easy for ComputersReview of PerformanceWhich is faster?DefinitionsComputer PerformanceCycles Per Instruction (Throughput)Example: Calculating CPI bottom upExample: Branch Stall ImpactSpeed Up Equation for PipeliningNow, Review of Memory HierarchyThe Memory AbstractionRecap: Who Cares About the Memory Hierarchy?Levels of the Memory HierarchyThe Principle of LocalityMemory Hierarchy: TerminologyCache MeasuresSimplest Cache: Direct Mapped1 KB Direct Mapped Cache, 32B blocksThe Cache Design SpaceRelationship of Caching and PipeliningComputer System ComponentsA Modern Memory HierarchyTLB, Virtual MemorySummarycpsc614Lec 1.1Based on Lectures by: Prof. David E CullerProf. David PattersonUC BerkeleyCPSC 614:Graduate Computer ArchitectureProf. Lawrence Rauchwerger Introductioncpsc614Lec 1.2Outline•Why Take CPSC 614?•Fundamental Abstractions & Concepts•Instruction Set Architecture & Organization•Administrivia•Pipelined Instruction Processing•Performance•The Memory Abstraction•Summarycpsc614Lec 1.3Why take CPSC 614?•To design the next great instruction set?...well...–instruction set architecture has largely converged–especially in the desktop / server / laptop space–dictated by powerful market forces•Tremendous organizational innovation relative to established ISA abstractions•Many New instruction sets or equivalent–embedded space, controllers, specialized devices, ...•Design, analysis, implementation concepts vital to all aspects of EE & CS–systems, PL, theory, circuit design, VLSI, comm.•Equip you with an intellectual toolbox for dealing with a host of systems design challengescpsc614Lec 1.4Example Hot Developments ca. 2002•Manipulating the instruction set abstraction–itanium: translate ISA64 -> micro-op sequences–transmeta: continuous dynamic translation of IA32–tinsilica: synthesize the ISA from the application–reconfigurable HW•Virtualization–vmware: emulate full virtual machine–JIT: compile to abstract virtual machine, dynamically compile to host•Parallelism–wide issue, dynamic instruction scheduling, EPIC–multithreading (SMT)–chip multiprocessors•Communication–network processors, network interfaces•Exotic explorations–nanotechnology, quantum computingcpsc614Lec 1.5Forces on Computer ArchitectureComputerArchitectureTechnologyProgrammingLanguagesOperatingSystemsHistoryApplications(A = F / M)cpsc614Lec 1.6Amazing Underlying Technology Changecpsc614Lec 1.7A take on Moore’s LawTra ns is to rs      1,00010,000100,0001,000,00010,000,000100,000,0001970 1975 1980 1985 1990 1995 2000 2005Bit-level parallelism Instruction-level Thread-level (?)i4004i8008i8080i8086i80286i80386R2000Pentium R10000R3000cpsc614Lec 1.8Technology Trends•Clock Rate: ~30% per year•Transistor Density: ~35%•Chip Area: ~15%•Transistors per chip: ~55%•Total Performance Capability: ~100%•by the time you graduate...–3x clock rate (3-4 GHz)–10x transistor count (1 Billion transistors)–30x raw capability•plus 16x dram density, 32x disk densitycpsc614Lec 1.9Performance0.11101001965 1970 1975 1980 1985 1990 1995SupercomputersMinicomputersMainframesMicroprocessorsPerformance Trendscpsc614Lec 1.10Measurement and EvaluationArchitecture is an iterative process -- searching the space of possible designs -- at all levels of computer systemsGood IdeasGood IdeasMediocre IdeasBad IdeasCost /PerformanceAnalysisDesignAnalysisCreativitycpsc614Lec 1.11What is “Computer Architecture”?I/O systemInstr. Set Proc.CompilerOperatingSystemApplicationDigital DesignCircuit DesignInstruction Set ArchitectureFirmware•Coordination of many levels of abstraction•Under a rapidly changing set of forces•Design, Measurement, and EvaluationDatapath & Control Layoutcpsc614Lec 1.12Coping with CPSC 614•Students with too varied background?•Review: CPSC 321 and/or “Computer Organization and Design (COD)2/e” –Chapters 1 to 8 of COD if never took prerequisite–If took a class, be sure COD Chapters 2, 6, 7 are familiar•FAST review this week of basic conceptscpsc614Lec 1.13Review of Fundamental Concepts•Instruction Set Architecture•Machine Organization•Instruction Execution Cycle•Pipelining•Memory•Bus (Peripheral Hierarchy)•Performance Iron Trianglecpsc614Lec 1.14The Instruction Set: a Critical Interfaceinstruction setsoftwarehardwarecpsc614Lec 1.15Instruction Set Architecture... the attributes of a [computing] system as seen by the programmer, i.e. the conceptual structure and functional behavior, as distinct from the organization of the data flows and controls the logic design, and the physical implementation. – Amdahl, Blaaw, and Brooks, 1964SOFTWARESOFTWARE-- Organization of Programmable Storage-- Data Types & Data Structures: Encodings & Representations-- Instruction Formats-- Instruction (or Operation Code) Set-- Modes of Addressing and Accessing Data Items and Instructions-- Exceptional Conditionscpsc614Lec 1.16OrganizationLogic Designer's ViewISA LevelFUs & Interconnect•Capabilities & Performance Characteristics of Principal Functional Units–(e.g., Registers, ALU, Shifters, Logic Units, ...)•Ways in which these components are


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TAMU CSCE 614 - lecture 01

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