6.004 Computation Structures - 1 - Lab #6 M A S S A C H U S E T T S I N S T I T U T E O F T E C H N O L O G Y DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE 6.004 Computation Structures Lab #6 Preparation: the description of the Beta implementation in lecture 15, the ALU function codes from Lab #3, and the Summary of Instruction Formats will be useful when working on this lab. Note: this is a long assignment, please plan accordingly! The goal of this lab is to complete your Beta design. We’ll do it in two steps: first get the design to the point where it can execute a “basic block” of instructions, i.e., a sequence of instructions that does not contain any branches or jumps. And second, add the circuitry to handle transfers of control (JMP, BNE, BEQ). The following diagram of a simplified Beta that can execute basic blocks shows what needs to be done for the first step: Dat a MemoryRD WD Adr R/W WDSEL01WARc : < 2 5: 21 >RESET PC +4 InstructionMemoryADRb : <15: 11>Ra : < 20: 16 >RA2SEL Rc : <25:2 1> Re g ist erFileRA 1 RA 2RD 1 RD 2BSEL 01C: <15:0>C: <15:0>sign-extendedALUABWAWD WE ALUFNControl Logic0 1Wr0 1 W E R F 00 PCREGFILECTL 0 OP: <31:26>RESET2ASELBSELPCSEL[2:0]RA 2 SELWDSEL[1:0]ALUFN[ 5:0]WrWASELWERF It’s probably best to tackle this step in stages. Here are some step-by-step design notes keyed to the dotted-line boxes in the block diagram shown above.6.004 Computation Structures - 2 - Lab #6 PC The 32-bit multiplexer selects the value to be loaded into the PC at next rising edge of the clock. Eventually the mux will have inputs used for implementing branches, jumps, exceptions, etc. but for now use a two-input 32-bit mux that selects 0x00000000 when the RESET signal is asserted, and the output of the PC+4 logic when RESET is not asserted. We will use the RESET signal to force the PC to zero during the first clock period of the simulation. The PC is a separate 32-bit register that can be built using the dreg component from the parts library. You should include hardware for the bottom two bits of the PC even though they are always 0; this will make debugging traces easier to interpret. Conceptually, the increment-by-4 circuit is just a 32-bit adder with one input wired to the constant 4. You can implement it this way, but it is possible to build a much smaller circuit if you design an adder optimized knowing that one of its inputs is 0x00000004. We’ve created a test jig to test your PC circuitry. Your netlist should incorporate the following three .include statements .include "/mit/6.004/jsim/nominal.jsim" .include "/mit/6.004/jsim/stdcell.jsim" .include "/mit/6.004/jsim/lab6pc.jsim" and the following subcircuit definition (you can of course define other subcircuits as well) .subckt pc clk reset ia[31:0] … your mux/register/+4 circuit here … .ends REGFILE The register file is a 3-port memory. Here’s a template netlist for specifying the 3-port register file: Xregfile + vdd 0 0 ra[4:0] adata[31:0] // A read port + vdd 0 0 ra2mux[4:0] bdata[31:0] // B read port + 0 clk werf rc[4:0] wdata[31:0] // write port + $memory width=32 nlocations=31 A more complete description of how to use the $memory JSim component can be found at the end of this writeup. Note that the memory component doesn’t know that location 31 of the register file should always read as zero, so you’ll have to add additional logic around the memory that makes this happen. You can use muxes or ANDs to force the register data for each read port to “0” when the port address = 0b11111 (i.e., R31). And you’ll need a mux controlled by RA2SEL to select the correct address for the B read port. We’ve created a test jig to test your register file circuitry. Your netlist should incorporate the following three .include statements6.004 Computation Structures - 3 - Lab #6 .include "/mit/6.004/jsim/nominal.jsim" .include "/mit/6.004/jsim/stdcell.jsim" .include "/mit/6.004/jsim/lab6regfile.jsim" and the following subcircuit definition (you can of course define other subcircuits as well) .subckt regfile clk werf ra2sel ra[4:0] rb[4:0] rc[4:0] + wdata[31:0] radata[31:0] rbdata[31:0] … your register file circuit here … .ends CTL The control logic should be tailored to generate the control signals your logic requires, which may differ from what’s shown in the diagram above. Note that a ROM can be built by specifying a memory with just one read port; the ROM contents are set up using the contents keyword in the netlist description of the memory. For example, the netlist for a ROM that uses the opcode field of the instruction to lookup the values for 18 control signals might look like: Xctl vdd 0 0 id[31:26] // one read port + pcsel[2:0] wasel asel ra2sel bsel alufn[5:0] wdsel[1:0] werf moe xwr + $memory width=18 nlocations=64 contents=( + 0b000000000000000000 // opcode=0b000000 + 0b000000000000000000 // opcode=0b000001 + … + ) Most of the signals can connected directly to the appropriate logic, e.g., ALUFN[5:0] can connect directly to the ALUFN inputs of your ALU. During this step, we won’t be using PCSEL[2:0], WASEL or ASEL, so you can set the corresponding bits in each ROM location to zero. We do need to be careful with the write enable signal for main memory (WR) which needs to be valid even before the first instruction is fetched from memory. So you should include some additional logic that forces WR to 0 when RESET=1 – the signal XWR from the ROM needs to combined appropriately with RESET to form WR. MOE is another memory control signal; see the next section for more information. We’ll be adding more bits to the control ROM when the branch logic is added in the next lab. For this lab, your design should implement the following instructions: LD, ST, ADD, SUB, CMPEQ, CMPLT, CMPLE, AND, OR, XOR, SHL, SHR, SRA, ADDC, SUBC, CMPEQC, CMPLTC, CMPLEC, ANDC, ORC, XORC, SHLC, SHRC, SRAC Eventually unimplemented instructions will cause an exception, but for now turn them into NOPs by making sure WERF is set to 0 (preventing any value from being written into a destination register).6.004 Computation Structures - 4 - Lab #6 If you’ve followed the scheme outlined above, we’ve created a test jig to test your control circuitry. Your netlist should incorporate the following three .include statements .include "/mit/6.004/jsim/nominal.jsim" .include
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