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MIT 16 01 - Computer Architecture

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Introduction to Computers and Programming Lecture 6 Recap Prof. I. K. Lundqvist Reading: B pp. 74-98 Sept 15 2003 • The Binary system • How to represent negative numbers • Why floating point numbers • How FPs are represented in a computer • Number representation –Integers – Real numbersof wires”) Computer Architecture computer architecture = computer organization + instruction set architecture von Neumann architecture computer processor ALU CU Reg Reg 10101101 … 01111000 Input Output bus • The Arithmetic Logic Unit (ALU) • The Control Unit • The memory • The input and output devices (I/O) memory devices How Computers Work • von Neumann architecture – Describes a computer with 4 main sections – The parts are connected by a bus (“bundleComputer Organization • CPU: central processing unit contained in the software – Arithmetic Logic Unit: performs operations such as addition, subtraction, bit-wise AND, OR, … – Control Unit: “directs the CPU’s operations” fetches instructions from memory, decodes them and produces signals which control the other parts of the computer Example 1: Adding values stored in memory computer processor ALU CU 10101101 … 01111000 Input bus 1. Get one of the values to be added from memory and place it in a register 2. Get the other value to be added from memory and place it in another register 3. Activate the addition circuitry with the registers used in 1 and 2 as inputs and another register designated to hold the result 4. Store the result in memory 5. Stop memory devices – Interprets and carries out the instructions Reg Reg OutputStorage Registers Cache Main memory Magnetic disk Magnetic tape>1TB 40GB 256MB 1MB < 1KB capacity 50 sec 5 ms 50 ns 2-5 ns 1 ns Access latency Input and Output information from the outside world, and send results of its work back again • Allows the computer to obtain • Device controllersHard drive controllerDevice Controllers CPU Memory Video controller DVD controller controller controller Memory mapped I/O Direct Memory Access (DMA) The von Neumann Bottleneck memory devices ALU CU Reg Reg 10101101 … 01111000 Input bus Fetch unit Decode unit Execute unit Pipelined CPU processor Hard drive controller USB Network • Cache memory computer Output • Other architectures – Pipelined CPU – Multiprocessor MachineInstruction Set Architecture • ISA: spec. detailing the commands a CPU should be able to understand and execute –… Instruction Set machine language instructions that a processor understands fields Hardware Software • add, sub, mult, …, how is it specified • 0, 1, 2, 3 • where besides memory • how is memory location specified • byte, integer, float, … Instruction Set –Operations – Number of operands –Operand storage – Memory address – Type and size of operands • The collection of • Instructions are bits with well definedMachine Language program Assembly language program Machine language program microprogram Microprogram execution (circuits) Compiler Assembler Control Pay := Amount1 + Amount2; LOAD R1,($2) LOAD R2,($4) ADD R2,R1,R2 STORE R2,($6) PCout, ARin, READ, DRout, R1in, PCinc ARin, READ ALU operation Instruction set • classified into 3 categories – Data transfer • – Arithmetic/logic • within the ALU (+, -, …, XOR, …, SHIFT, ROTATE) – Control • – – RISC / CISC High level language Control signal spec. or Machine interpretation Instructions in a machine’s repertoire can be • I/O instructions Instructions that tell the CU to request an activity Instructions that direct the execution of the program Conditional jumps Unconditional jumps 0000 0011 0011 0100 1101 1110 1001 0001 1011 1101 1100 0100 LOAD / STOREDividing values stored in memory described in Appendix C The architecture of the machine CPU 00 01 02 03 FF Bus 0 1 2 F . . . . . . . . . . Program counter Instruction register Main memory Address Cells Registers Arithmetic / Logic Unit Control Unit LOAD a register with a value from memory. STEP 1. STEP 2. STEP 3. STEP 4. STEP 5. STEP 6. LOAD another register with another value from memory. STORE the contents of the third register in memory. STOP. If this second value is zero, JUMP to step 6. Divide the contents of the first register by the second register and leave the result in a third register.The composition of an instruction for the machine in Appendix C Decoding the instruction 35A7 3 5 A 7 0011 0101 1010 0111 3 5 A 7[ [ to store the contents Op-code Operand 16-bit pattern 4-digit hexadecimal form Instruction Op-code 3 means of a register in a memory cell. This part of the operand identifies the register whose contents are to be stored. This part of the operand identifies the address of the memory cell that is to receive


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MIT 16 01 - Computer Architecture

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