14:332:331 Computer Architecture and Assembly Language Spring 2006 Week 11: MicroprogrammingSimplifying Control DesignMicroprogrammingDefining a Microinstruction FormatReview: Multicycle Data and Control PathReview: Multicycle RTL SummaryOur Microinstruction FormatOur Microinstruction Format, con’tDispatch (Branch) LogicCreating the MicroprogramSlide 12Slide 14Slide 16Slide 18The Entire Control MicroprogramMicroprogram to MicrocodeMicrocode ImplementationAddress Select LogicReview: FSM ImplementationControl Path Design AlternativesWeek 11 Spring 200614:332:331Computer Architecture and Assembly LanguageSpring 2006Week 11: Microprogramming[Adapted from Dave Patterson’s UCB CS152 slides andMary Jane Irwin’s PSU CSE331 slides]Week 11 Spring 2006Simplifying Control DesignFor an implementation of the full MIPS ISAinstructions can take from 1 clock cycle to 20 clock cyclesresulting in finite state machines with hundreds to thousands of states with even more arcs (state sequences)Graphical representations become impossibly complexInstead, represent the set of control signals that are asserted during a state as a low-level control “instruction” to be executed by the datapathmicroinstructions“Executing” the microinstruction is equivalent to asserting the control signals specified by the microinstructionWeek 11 Spring 2006MicroprogrammingMicroinstruction has to specifywhat control signals should be assertedwhat microinstruction should be executed nextEach microinstruction corresponds to one state in the FSM and is assigned a state number (or “address”)1. Sequential behavior – increment the state (address) of the current microinstruction to get to the state (address) of the next2. Jump to the microinstruction that begins execution of the next MIPS instruction (state 0)3. Branch to a microinstruction based on control unit input using dispatch tables-need one for microinstructions following state 1-need another for microinstructions following state 2The set of microinstructions that define a MPS assembly language instruction (macroinstruction) is its microroutineWeek 11 Spring 2006Defining a Microinstruction FormatFormat – the fields of the microinstruction and the control signals that are affected by each fieldcontrol signals specified by a field usually have functions that are relatedformat is chosen to simplify the representation and to make it difficult to write inconsistent microinstructions-i.e., that allow a given control signal be set to two different valuesMake each field of the microinstruction responsible for specifying a nonoverlapping set of control signalssignals that are never asserted simultaneously may share the same fieldseven fields for our simple machine-ALU control; SRC1; SRC2; Register control; Memory; PCWrite control; SequencingWeek 11 Spring 2006Review: Multicycle Data and Control PathAddressRead Data(Instr. or Data)MemoryPCWrite DataRead Addr 1Read Addr 2Write AddrRegisterFileRead Data 1Read Data 2ALUWrite DataIRMDRABALUoutSignExtendShiftleft 2ALUcontrolShiftleft 2ALUOpControlFSMIRWriteMemtoRegMemWriteMemReadIorDPCWritePCWriteCondRegDstRegWriteALUSrcAALUSrcBzeroPCSource1111110000002234Instr[5-0]Instr[25-0]PC[31-28]Instr[15-0]Instr[31-26]3228Week 11 Spring 2006Review: Multicycle RTL SummaryStep R-type Mem Ref Branch JumpInstr fetchIR = Memory[PC]; PC = PC + 4;DecodeA = Reg[IR[25-21]];B = Reg[IR[20-16]];ALUOut = PC +(sign-extend(IR[15-0])<< 2);ExecuteALUOut = A op B;ALUOut = A + sign-extend (IR[15-0]);if (A==B) PC = ALUOut; PC = PC[31-28] ||(IR[25-0] << 2);Memory accessReg[IR[15-11]] = ALUOut;MDR = Memory[ALUOut]; orMemory[ALUOut] = B; Write-backReg[IR[20-16]] = MDR;Week 11 Spring 2006Our Microinstruction FormatField Value Signal setting CommentsALU controlAdd ALUOp = 00 Cause ALU to addSubt ALUOp = 01 Cause ALU to subtract (compare op for beq)Func code ALUOp = 10 Use IR function code to determine ALU controlSRC1 PC ALUSrcA = 0 Use PC as top ALU inputA ALUSrcA = 1 Use reg A as top ALU inputSRC2 B ALUSrcB = 00 Use reg B as bottom ALU input4 ALUSrcB = 01 Use 4 as bottom ALU inputExtend ALUSrcB = 10 Use sign extension output as bottom ALU inputExtshft ALUSrcB = 11 Use shift-by-two output as bottom ALU inputRegister controlRead Read RegFile using rs and rt fields of IR as read addr’s; put data into A and BWrite ALU RegWrite, RegDst = 1, MemtoReg = 0Write RegFile using rd field of IR as write addr and ALUOut as write dataWrite MDR RegWrite, RegDst = 0, MemtoReg = 1Write RegFile using rt field of IR as write addr and MDR as write dataWeek 11 Spring 2006Our Microinstruction Format, con’tField Value Signal setting CommentsMemory Read PC MemRead, IorD = 0,IRWriteRead memory using PC as addr; write result into IR (and MDR)Read ALU MemRead, lorD = 1Read memory using ALUOut as addr; write results into MDRWrite ALU MemWrite, IorD = 1Write memory using ALUOut as addr and B as write dataPC write controlALU PCSource = 00 PCWriteWrite PC with output of ALUALUOut-condPCSource = 01, PCWriteCondIf Zero output of ALU is true, write PC with the contents of ALUOutJump addressPCSource = 10, PCWriteWrite PC with IR jump address after shift-by-twoSequen-cingSeq AddrCtl = 11 Choose next microinstruction sequentiallyFetch AddrCtl = 00 Jump to the first microinstruction (i.e., Fetch) to begin a new instructionDispatch 1 AddrCtl = 01 Branch using PLA_1Dispatch 2 AddrCtl = 10 Branch using PLA_2Week 11 Spring 2006Dispatch (Branch) LogicDispatch operations are implemented using special logic (PLAs)Microcode Dispatch PLA_1Opcode fieldOpcode Value (Addr)000000 R-format Rexec (6)000010 jmp Jump (9)000100 beq Beq (8)100011 lw Maddr (2)101011 sw Maddr (2)Microcode Dispatch PLA_2Opcode fieldOpcode Value (Addr)100011 lw Memlw (3)101011 sw Memsw (5)Week 11 Spring 2006Creating the MicroprogramFetch microinstructionLabel (Addr)ALU controlSRC1 SRC2 Reg controlMemory PCWrite controlSeq’ingFetch (0)Add PC 4 Read PC ALU Seqcompute PC + 4fetch instr into IRwrite ALU output into PCgo to instr 1Label field represents the state (address) of the microinstructionFetch microinstruction assigned state (address) 0Week 11 Spring 2006Creating the Microprogram, con’tDecode microinstructionLabel (Addr)ALU controlSRC1 SRC2 Reg controlMemory PCWrite controlSeq’ingDecode (1)Add PC Ext shftRead Disp 1compute branch target (PC + sign_ext(IR[15-0])<<2)) and store it in