tocA 21-mW 8-b 125-MSample/s ADC in 0.09- $\hbox{mm}^{2}$ 0.13- $\mJan Mulder, Christopher M. Ward, Chi-Hung Lin, David Kruse, Jan I. I NTRODUCTIONII. ADC A RCHITECTUREFig. 1. Two-step subranging ADC architecture.Fig. 2. Architecture of the CADC.III. C OARSE ADCFig. 3. Schematic of the amplifier used in the CADC.IV. F INE ADCV. O FFSET C OMPENSATIONFig. 4. Block diagram of the FADC.Fig. 5. Operation principle of the FADC.VI. P IPELININGFig. 6. Simplified schematic of the reset switches in array $ {AFig. 7. Effect of finite on-resistance of the reset switches at Fig. 8. Implementation of the reset switches in array $ {A}$ andVII. I NTERPOLATIONFig. 9. Implementation of 2 $\times $ interpolation of the referFig. 10. Implementation of another 2 $\times $ capacitive interpA. Reference Ladder InterpolationB. FADC InterpolationFig. 11. Simplified schematic of a differential-pair amplifier pVIII. A VERAGINGFig. 12. Implementation of 2 $\times $ capacitive averaging.IX. T IMINGFig. 13. Distributed averaging topology, providing 4 $\times $ aFig. 14. Timing diagram of the ADC.Fig. 15. Microphotograph of the ADC.X. E XPERIMENTAL R ESULTSTABLE I P ERFORMANCE S UMMARYFig. 16. Measured histogram of FADC output codes.Fig. 17. Measured INL and DNL.Fig. 18. Measured ADC performance versus $f_{\rm clk}$ at $f_{\rFig. 19. Measured ADC performance versus $f_{\rm in}$ at $f_{\rmFig. 20. Measured output spectrum of the ADC.TABLE II P ERFORMANCE C OMPARISONXI. C ONCLUSIONY. Yoshii, K. Asano, M. Nakamura, and C. Yamada, An 8 bit, 100 MA. Matsuzawa, Y. Kitagawa, I. Hidaka, S. Sawada, M. Kagawa, and C. S. G. Conroy, D. W. Cline, and P. R. Gray, An 8-b 85-MS/s parW. Bright, 8 b 75 MSample/s 70 mW parallel pipelined ADC incorpoK. Irie, N. Kusayanagi, T. Kawachi, T. Nishibu, and Y. MatsumoriJ. Ming and S. H. Lewis, An 8-bit 80-Msample/s pipelined analog-K. Poulton, R. Neff, A. Muto, W. Liu, A. Burstein, and M. HeshamK. Poulton, R. Neff, N. Setterberg, B. Wuppermann, T. Kopley, R.S. Limotyrakis, S. D. Kulchycki, D. Su, and B. A. Wooley, A 150 B. Nauta and A. G. W. Venes, An 70-MS/s 110-mW 8-b CMOS folding C. W. Moreland, An 8 b 150 MSample/s serial ADC, in ISSCC Dig. TA. G. W. Venes and R. J. van de Plassche, An 80-MHz, 80-mW, 8-b M. P. Flynn and D. J. Allstot, CMOS folding A/D converters with K. Yoon, J. Lee, D.-K. Jeong, and W. Kim, An 8-bit 125 MS/s CMOSM.-J. Choe, B.-S. Song, and K. Bacrania, An 8-b 100-MSample/s CMG. Geelen and E. Paulus, An 8 b 600 MS/s 200 mW CMOS folding A/DR. Taft, C. Menkus, M. R. Tursi, O. Hidri, and V. Pons, A 1.8 V Y. Nishida, K. Sone, K. Amano, S. Matsuba, and A. Yukawa, An 8-bM. Sugawara, Y. Yoshida, M. Mitsuishi, S. Nakamura, S. NakaigawaY.-T. Wang and B. Razavi, An 8-bit 150-MHz CMOS A/D converter, IR. C. Taft and M. R. Tursi, A 100-MS/s 8-b CMOS subranging ADC wR. C. Taft, M. R. Tursi, and A. Glenny, Design techniques for veJ. Mulder, C. M. Ward, C.-H. Lin, D. Kruse, J. R. Westra, M. L. A. G. F. Dingwall and V. Zazzu, An 8-MHz CMOS subranging 8-bit AT. Matsuura, H. Kojima, E. Imaizumi, K. Usui, and S. Ueda, An 8-K. Kusumoto, A. Matsuzawa, and K. Murata, A 10-b 20-MHz 30-mW piB. P. Brandt and J. Lutsky, A 75-mW, 10-b, 20-MSPS CMOS subrangiH. van der Ploeg, G. Hoogzaad, H. A. H. Termeer, M. Vertregt, anM. Clara, A. Wiesbauer, and F. Kuttner, A 1.8 V fully embedded 1K. Nagaraj, F. Chen, T. Le, and T. R. Viswanathan, Efficient 6-bM.-J. Choe, B.-S. Song, and K. Bacrania, A 13-b 40-MSaples/s CMOT. Sigenobu, M. Ito, and T. Miki, An 8-bit 30 MS/s 18 mW ADC witP. Vorenkamp and R. Roovers, A 12-b, 60-MSample/s cascaded foldiM. P. Flynn and B. Sheahan, A 400-Msample/s, 6-b CMOS folding anG. Hoogzaad and R. Roovers, A 65-mW, 10-bit, 40-Msample/s BiCMOSH. van der Ploeg and R. Remmers, A 3.3-V, 10-b, 250 MSample/s twK. Sushihara and A. Matsuzawa, A 7 b 450 MSample/s 50 mW CMOS ADK. Kattmann and J. Barrow, A technique for reducing differentialK. Yoon, S. Park, and W. Kim, A 6 b 500 MSample/s CMOS flash ADCP. Scholtens and M. Vertregt, A 6 b 1.6 GSample/s flash ADC in 0K. Bult and A. Buchwald, An embedded 240-mW 10-b 50-MS/s CMOS ADH. Pan, M. Segami, M. Choi, J. Cao, and A. A. Abidi, A 3.3-V 12-M. Choi and A. Abidi, A 6-b 1.3-Gsample/s A/D converter in 0.35-2116 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 12, DECEMBER 2004A 21-mW 8-b 125-MSample/s ADC in 0.09-mm20.13-m CMOSJan Mulder, Christopher M. Ward, Chi-Hung Lin, David Kruse, Jan R. Westra, Marcel Lugthart, Erol Arslan,Rudy J. van de Plassche, Fellow, IEEE, Klaas Bult, Member, IEEE, and Frank M. L. van der GoesAbstract—This paper presents an 8-b two-step subranginganalog-to-digital (ADC) using interpolation, averaging, offsetcompensation, and pipelining techniques to accomplish an ef-fective number of bits of 7.6 b at 125 MSample/s. The 0.13-mCMOS ADC occupies 0.09 mm2and consumes 21 mW.Index Terms—Analog-to-digital conversion, CMOS analogintegrated circuits (ICs), subranging analog-to-digital converter(ADC).I. INTRODUCTIONAREA and power are important parameters for analog-to-digital converters (ADCs) integrated on large digital ICs.This is especially true if several ADCs have to be implementedon the same die. These embedded ADCs necessarily have to bedesigned in state-of-the-art digital CMOS processes and, there-fore, have to work at low supply voltages, while special processoptions, such as low-threshold devices, are often not available.The ADC presented in this paper has 8-b resolution andsamples at a rate of 125 MSample/s. Several ADC architecturesare capable of achieving these specifications, e.g., flash ADCs[1], [2], pipeline ADCs [3]–[9], folding ADCs [10]–[17],and subranging ADCs [18]–[23]. However, when small diearea and low-power and low-voltage operation are of primaryimportance, the two-step subranging architecture has proven tobe a very suitable choice. A key advantage of this architectureis that the two-step approach allows for an area- and power-ef-ficient design. Additionally, it can use simple differential-pairamplifiers, which are very well fit for low-voltage operation.The basic architecture of the two-step subranging ADC, com-prising a coarse ADC (CADC) and a fine ADC (FADC), is ex-plained in Section II. The design of the CADC is described inSection III. Section IV first gives an overview of the FADC de-sign, followed in Sections V–VIII by a detailed discussion of thetechniques used in the FADC: offset compensation, pipelining,interpolation, and averaging, respectively. Section IX