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Outline Transmitters Chapters 3 and 4 Source Coding and Modulation week 1 and 2 Receivers Chapter 5 week 3 and 4 Received Signal Synchronization Chapter 6 week 5 Channel Capacity Chapter 7 week 6 Error Correction Codes Chapter 8 week 7 and 8 Equalization Bandwidth Constrained Channels Chapter 10 week 9 Adaptive Equalization Chapter 11 week 10 and 11 Spread Spectrum Chapter 13 week 12 Fading and multi path Chapter 14 week 12 Received Signal Synchronization Chapter 6 week 5 Receiver needs Carrier Phase Estimation Phase Locked Loops Decision Directed Loops Symbol Timing Estimation Digital Communication System Transmitter Receiver Signal Parameter Estimation Propagation Delay phase and timing error r t s t n t received signal Re sl t e j 2 f ct n t delay noise 2 f c d 2 f c 2 kHz GHz d large so phase very sensitive Need separate estimators Phase Estimation very narrow bandwidth slow tracks sending fc very accurate Timing Estimation tracks changes in delay faster less accurate QAM Phase Estimation s M T dt 0 T dt 0 Timing Estimation s1 Select si for which d 2 g sm1 si 2 s1 Select si for which d 2 g 2 sm 2 si Maximum Likelihood Estimates Likelihood function maximized if best estimate made Assume white Gaussian noise r r1 r2 rN 1 N max p r max exp 2 rn sn 2 2 2 n 1 N N rn sn 2 lim max p r exp lim 2 N N 2 n 1 1 2 exp r t s t dt N 0 T0 Maximum Likelihood Carrier Phase Estimate Assume Then ML function is 1 2 max max exp r t s t dt N 0 T 0 1 2 1 2 2 max exp r t dt r t s t dt s t dt N N N 0 0 0 T T T 0 0 0 2 max r t s t dt N0 T 0 Maximum Likelihood Carrier Phase Estimate A necessary condition yields 2 max r t s t dt N 0 T 0 d r t s t dt T0 0 d ML ds t r t dt 0 d ML T0 Maximum Likelihood Carrier Phase Estimate Implementing this ds t r t dt 0 d ML T0 r t T dt 0 ds t d ML dt If the loop is stable then this is a ML estimate Maximum Likelihood Carrier Phase Estimate Phase Locked Loop Loop filter r t T dt 0 ds t d ML dt Voltage Controlled Oscillator VCO Phase Locked Loop Using an unmodulated carrier for s t and a simple loop filter r t 1 1s 1 2 s sin 2 f ct K s Phase Locked Loop Using the phase of low pass equivalents and linearizing 1 2 s 1 1s K s 1 2 s H s 1 2 1 K s 1 K s 2 K 1 2 s s 1 1s K 1 2 s K 1 2 s s 1 1s s 1 1s K 1 2 s K 1 2 s 1 s 1 1s s 1 1s K 1 2 s K 1 2 s s 1 1s 1 2 s 1 2 s 1 Ks 1 Ks 2 Stable second order system Effect of noise on phase estimate Gaussian noise added at input N0 2 Ac 2 H f 0 2 df N 0 Beq Ac2 1 SNR s t Ac cos 2 f c t t Equivalent linear system Phase Locked Loop Nice damping and H s 2 n 2 4 1 1 2 s n K 1 2 1 2 2 n 2 n n s s n n 2 1 K 2 1 0 n 2 2 1 K n2 K 1 K n2 1 n 2 2 1 n2 1 n2 2 1 2 1 n 1 0 n 2 2 2 n 2 2 1 0 ax 2 bx c 0 x b b 2 4ac 2a n 2 2 4 4 2 1 2 2 1 no solution Phase Locked Loop Stable second order system 2 1 Pole and zero cancel K s Not second order K n K K s s K K 1 s s K K s 1 1 s K Phase Locked Loop Effect of noise on phase estimate 2 1 2 Beq H f df 0 K n 2 1 df 0 1 j 2 f K 1 df 0 1 2 f K 2 K 2 arctan 2 f K 0 K 2 arctan K K 2 arctan 0 K K 2 2 K 4 Gain large noise bandwidth small Phase Locked Loop Nice damping and 1 2 1 2 s n2 H s 2 n K 1 n 2 n n s s 2 n n 2 1 K 2 1 0 K 1 2 n 2 2 2 n 1 K 1 n 2 2 1 K 2 1 n 1 K n 1 2 n2 K 1 K n2 1 n 2 2 1 n2 1 2 1 1 n n 1 2 n2 2 1 2 1 n 1 0 2 1 1 n 1 n n2 2 2 n 1 1 0 2 1 n 1 2 1 n 1 2 n2 2 2 n 1 1 0 ax 2 bx c 0 x b b 2 4ac 2a n 2 4 4 2 2 2 1 1 2 0 2 2 2 1 K n2 1 4 1 22 1 2 1 2 2 1 4 n 2 2 K 4 1 n K 1 1 1 2 2 n n 2 1 K 2 1 1 2 4 1 n 2 4 1 2 1 2 n 1 1 1 Phase Locked Loop Conditions for nice damped system 1 2 n 2 2 K 4 1 2 2 or 1 2 1 4 n K 1 2 1 1 Phase Locked Loop Effect of noise on phase estimate 1 2 2 Beq H f df 0 1 K 22 1 4 2 1 K 1 4 K 4 1 22 2 n 1 2 n 4 2 1 2 4 1 5 2 1 4 2 5 n n 2 2 8 Gain very large noise bandwidth OK Phase Locked Loop Effect of noise on phase estimate 1 2 2 Beq H f df 0 1 K 22 1 4 2 1 K 1 22 4 12 1 4 K 1 2 4 2 1 1 4 2 1 1 2 1 1 1 2 n n 2 1 Gain low noise bandwidth high Phase Locked Loop Summary of effect of noise on phase estimate Best two cases 5 n Beq K 4 1 22 2 n 1 2 n n 2 2 2 1 8 r t n Beq K n 2 1 4 1 1s 1 2 s sin 2 f c t K s Decision Directed Loops PLLs have problems when the signal is imposed on the carrier and carrier is no longer part of signal This is very efficient for power so is usually the case in power …


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Duke ECE 283 - Outline

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