Stanford EE 392C - Lecture #7 - Polymorphic Architectures I (6 pages)

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Lecture #7 - Polymorphic Architectures I



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Lecture #7 - Polymorphic Architectures I

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Pages:
6
School:
Stanford University
Course:
Ee 392c - Advanced Topics in Computer Architecture

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EE392C Advanced Topics in Computer Architecture Polymorphic Processors Stanford University Lecture 7 Tuesday April 29 2003 Polymorphic Architectures I Lecture 7 Lecturer Scribe Tuesday April 22 2003 Jing Jiang and Honggo Wijaya Chi Ho Yue and Rohit Gupta We are entering an era of ubiquitous computing as technology scales more and more applications demand ever growing performances Yet the design complexity grows as well In addition high non incurring fabrication cost and manufacturing delays demand chips to be sold in large volume thus targeting a larger market to be cost effective How can we achieve performances comparable to customized solutions in a single chip design The answer is Polymorphous Architecture One thing is for sure interconnect is going to be a big issue and therefore any kind of architecture needs to be scalable in terms of wires We will look at 2 particular solutions today Smart memories and TRIPS 1 Paper 1 The TRIPS Multiprocessor TRIPS processor consists 4 out of order 16 wide issue Grid processor cores which can be partitioned to exploit different types of parallelism It uses software scheduler to optimize for point to point communication It s a block oriented system in all modes of operations namely hyberblocks Programs are compiled into large blocks of instructions with single entry point no internal loops and possible multiple exit points Each block has a set of state inputs and a potentially variable set of state outputs that depend upon the exit point from the block The compiler is responsible for statically scheduling each block of instructions onto the computation engine Each node of the grid processor consists of an integer ALU A floating point unit a set of reservation states Each node can forward the result to any of the operands in the local of remote reservation states within the ALU TRIPS processor has the following resources to achieve configurability First frame space is the reservation stations with the same index across all



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