UE EE 254 - EE 254 Sample Test 4

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EE 254 Sample Test 4Open book, open notes, no computers.1. Three tri-state bi-directional registers R1, R2, and R3 are connected to a common bus. R1 has load input load 1 and tri-state enable input enable 1. R2 and R3 have tri-state enables and loads respectively. Assume the initial contents of the registers are as follows: R1 = 5, R2 = 6, R3 = 7. The waveform below indicates the signals that are applied to the registers. t1, t2, and t3 are time markers. Complete the table showing thecontents of the registers at the indicated time marks.2. Design a 3-bit counter using rising edge triggered j-k master-slave flip-flops with thecounting sequence ... 1,4,2,7,1,4,2,7, ... Use the outputs of the flip-flops as the output ofthe counter (Moore design). Construct a state table showing the present state and thenext state including any don’t cares marked with x’s. Construct the K-maps andminimize the logic needed to produce the counter. Sketch the circuit and check forLOCKOUT. If a lockout problem exists DO NOT FIX IT just list the states that cause theproblem.R1 R2 R3t1t2t33. The partial Verilog code to the right is used to create an 8-bitshift register. The shift register has clock s, data in d, andan 8 bit Q output. Complete the Verilog code.4. Given below is a 3 to 8 decoder with active low outputs, three address inputs A, B, C, one active high and two active low enable inputs G1, G2A, and G2B respectively. U1, U2, and U3 are I/O devices with active low chip selects as shown. There are six low order addresses A0, A1, A2, A3, A4, and A5 with A0 being the least significant bit. Place the appropriate address bits (A0, A1, A2, A3, A4, and A5) on the decoder inputs, and connect the appropriate decoder outputs to the I/O devices so that the I/O devices have the following addresses:U1 @ 20 hex U2 @ 30 hex U3 @ 3C hexmodule shift(s, d, Q); always@ ( ) begin end endmodule5. Answer the questions below about the Verilog code shown.A) What is the counting sequence for this counter assuming that it is reset on start up?B) Does this counter have lock out? C) What does state 12 = 1100 map into (next state)?D) You can eliminate at least one line from the case statement without changing the logical function. What is it?//Exam4.vmodule Exam4(clk, reset, state); parameter n = 4; input clk, reset; output [n-1:0]state; reg [n-1:0]state; // always @(posedge clk) if(reset) state = 0; else begin case (state) 4'b0000:state = 4'b0001; //0 -> 1 4'b0001:state = 4'b0100; //1 -> 4 4'b0010:state = 4'b0001; //2 -> 1 4'b0100:state = 4'b1010; //4 -> 10 4'b1001:state = 4'b1010; //9 -> 10 4'b1010:state = 4'b0101; //10-> 5 4'b0101:state = 4'b0110; //5 -> 6 4'b0110:state = 4'b0000; //6 -> 0 4'b1000:state = 4'b0001; //8 -> 1 default:state = 4'b0000; endcase end endmodule6. Given a memory system, which has 128K of 16-bit words. Answer the following:A) How many address lines does it take to address any word in memory? __________________________________________B) If the memory is constructed of 64K X 8 chips how many chips are used? ___________________________________________7. Given the Verilog module to the right with the signals inputted to the module as shown below:Complete the waveform for Q as indicated below.Q is initially 0.module what_is_it(D, CLK, Q); input clk, D; output Q; reg Q; always@(negedge CLK or posedge CLR) begin if (CLR) Q <= 0; else Q <= D; end


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UE EE 254 - EE 254 Sample Test 4

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