UE EE 254 - EE 254 Sample Test 4 (4 pages)

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EE 254 Sample Test 4



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EE 254 Sample Test 4

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Pages:
4
School:
University of Evansville
Course:
Ee 254 - Logic Design
Logic Design Documents

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EE 254 Sample Test 4 Open book open notes no computers 1 Three tri state bi directional registers R1 R2 and R3 are connected to a common bus R1 has load input load 1 and tri state enable input enable 1 R2 and R3 have tristate enables and loads respectively Assume the initial contents of the registers are as follows R1 5 R2 6 R3 7 The waveform below indicates the signals that are applied to the registers t1 t2 and t3 are time markers Complete the table showing the contents of the registers at the indicated time marks R1 R2 R3 t1 t2 t3 2 Design a 3 bit counter using rising edge triggered j k master slave flip flops with the counting sequence 1 4 2 7 1 4 2 7 Use the outputs of the flip flops as the output of the counter Moore design Construct a state table showing the present state and the next state including any don t cares marked with x s Construct the K maps and minimize the logic needed to produce the counter Sketch the circuit and check for LOCKOUT If a lockout problem exists DO NOT FIX IT just list the states that cause the problem 3 The partial Verilog code to the right is used to create an 8 bit shift register The shift register has clock s data in d and an 8 bit Q output module shift s d Q Complete the Verilog code always begin end endmodule 4 Given below is a 3 to 8 decoder with active low outputs three address inputs A B C one active high and two active low enable inputs G1 G2A and G2B respectively U1 U2 and U3 are I O devices with active low chip selects as shown There are six low order addresses A0 A1 A2 A3 A4 and A5 with A0 being the least significant bit Place the appropriate address bits A0 A1 A2 A3 A4 and A5 on the decoder inputs and connect the appropriate decoder outputs to the I O devices so that the I O devices have the following addresses U1 20 hex U2 30 hex U3 3C hex 5 Answer the questions below about the Verilog code shown A What is the counting sequence for this counter assuming that it is reset on start up B Does this counter have lock out C



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