UWMadison ECE 734  Exploring realizations of large integer multipliers using embedded blocks in modern FPGAs (4 pages)
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Exploring realizations of large integer multipliers using embedded blocks in modern FPGAs
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 University of Wisconsin, Madison
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 Ece 734  VLSI Array Structures for Digital Signal Processing
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Unformatted text preview:
ECE 734 Project Proposal Exploring realizations of large integer multipliers using embedded blocks in modern FPGAs Shreesha Srinath Motivation Multiplication functions constitute the kernel of many real life applications They are used extensively in applications such as digital signal processing image processing cryptography and multimedia 1 2 3 Recent computing oriented FPGAs feature embedded DSP blocks including small embedded multipliers Achieving efficient realization of multiplication may have significant impact on the specific application in terms of speed power dissipation and area FPGA vendors are now offering hardwired multipliers as one of the resources available to designers Examples could be that of Xilinx Spartan 3 Family which includes 104 on chip 18x18 multipliers and Xilinx Virtex 5 6 Family which include 25x18 multipliers Optimized realizations of large multipliers of large integer multipliers using such blocks are studied in 4 5 6 This project aims to study different approaches to implement large integer multipliers on DSP blocks in an efficient manner in terms of both timing and area Related Work In 4 5 the authors present an efficient design methodology and systematic approach for implementation of multiplication and squaring functions They propose a general architecture and a set of equations are derived to aid in realization The method used is that of the Divide and Conquer Algorithm 7 with efficient organization of partial products The symmetric embedded block considered is of size n X n and operands of size k such that n X m 1 k n X m The Table 1 below gives the sizes in bits of the partial products in the multiplication expression of two operands X and Y The authors then look at timing and area efficient organization of the additions of partial products including the method of deferred parallel carry addition of partial products in which the set of carry bits generated from various levels of partial product additions are combined and
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