Combinationalcircuit⭈⭈⭈⭈⭈⭈n inputs m outputsFig. 4-1 Block Diagram of Combinational Circuit© 2002 Prentice Hall, Inc.M. Morris ManoDIGITAL DESIGN, 3e.Fig. 4-2 Logic Diagram for Analysis ExampleABABCABCACBCF2F1T3T2T1F⬘2© 2002 Prentice Hall, Inc.M. Morris ManoDIGITAL DESIGN, 3e.000111100 1A CDBAB0 0CD11 10X1XX1X1 X1X1000111100 1A CDBAB0 0CD11 1011XXXX1 X1X1z  D y  CD  CD000111100 1A CDBAB0 0CD11 10111XXXX1 XX1X  BC  BD  BCD w  A  BC  BD000111100 1A CDBAB0 0CD11 10X1XXXXX1111Fig. 4-3 Maps for BCD to Excess-3 Code Converter© 2002 Prentice Hall, Inc.M. Morris ManoDIGITAL DESIGN, 3e.xzywDC ⫹D(C ⫹D)⬘CDD⬘CBAFig. 4-4 Logic Diagram for BCD to Excess-3 Code Converter© 2002 Prentice Hall, Inc.M. Morris ManoDIGITAL DESIGN, 3e.xyxyxySCxySC(a) S  xy  xy C  xy(b) S  x  y C  xyFig. 4-5 Implementation of Half-Adder© 2002 Prentice Hall, Inc.M. Morris ManoDIGITAL DESIGN, 3e.00 0 0 1x 1yzxyz11 101111S  x y z  x yz  xy z  xyz00 0 0 1x 1yzxyz11 101111S  xy  xz  yz  xy  xy z  x yz Fig. 4-6 Maps for Full Adder© 2002 Prentice Hall, Inc.M. Morris ManoDIGITAL DESIGN, 3e.xyxzyzCx⬘y⬘zx⬘yz⬘xy⬘z⬘xyzSFig. 4-7 Implementation of Full Adder in Sum of Products© 2002 Prentice Hall, Inc.M. Morris ManoDIGITAL DESIGN, 3e.xyzSCFig. 4-8 Implementation of Full Adder with Two Half Adders and an OR Gate© 2002 Prentice Hall, Inc.M. Morris ManoDIGITAL DESIGN, 3e.B3C4S3A3FAB2C3S2A2FAB1C2S1A1FAB0C1S0A0FAC0Fig. 4-9 4-Bit Adder© 2002 Prentice Hall, Inc.M. Morris ManoDIGITAL DESIGN, 3e.SiCi ⫹ 1AiPiGiBiCiFig. 4-10 Full Adder with P and G Shown© 2002 Prentice Hall, Inc.M. Morris ManoDIGITAL DESIGN, 3e.C3C2C1P2G2P1G1P0G0C0Fig. 4-11 Logic Diagram of Carry Lookahead Generator© 2002 Prentice Hall, Inc.M. Morris ManoDIGITAL DESIGN, 3e.B3P3P3G3P2P2G2P1P1G1P0P0G0C0A3C3S3C4C4C2S2C1S1S0B2A2B1A1B0A0C0CarryLook aheadgeneratorFig. 4-12 4-Bit Adder with Carry Lookahead© 2002 Prentice Hall, Inc.M. Morris ManoDIGITAL DESIGN, 3e.B3C4CVS3A3FAB2C3S2A2FAB1C2S1A1FAB0C1S0A0FAC0MFig. 4-13 4-Bit Adder Subtractor© 2002 Prentice Hall, Inc.M. Morris ManoDIGITAL DESIGN, 3e.OutputcarryCarryoutCarryinAddend Augend4- bit binary adder4- bit binary adderK0Z8Z4Z2Z1S8S4S2S1Fig. 4-14 Block Diagram of a BCD Adder© 2002 Prentice Hall, Inc.M. Morris ManoDIGITAL DESIGN, 3e.HA HAC3B1A1A0B0B1B0C2C1C0B1C3C2C1C0B0A1A1B1A1B0A0B1A0B0A0Fig. 4-15 2-Bit by 2-Bit Binary Multiplier© 2002 Prentice Hall, Inc.M. Morris ManoDIGITAL DESIGN, 3e.B3A0A1B2B1B0B3B2B1B0B3B2B1B00Addend AugendAugendSum and output carry4-bit adderA2AddendSum and output carry4-bit adderC2C1C0C3C4C5C6Fig. 4-16 4-Bit by 3-Bit Binary Multiplier© 2002 Prentice Hall, Inc.M. Morris ManoDIGITAL DESIGN, 3e.(A ⬍ B)(A ⬎ B)(A ⫽ B)x3A3B3A2B2A1B1A0B0x2x1x0Fig. 4-17 4-Bit Magnitude Comparator© 2002 Prentice Hall, Inc.M. Morris ManoDIGITAL DESIGN, 3e.D0  x y z D1  x y zD2  x yz D3  x yz D4  xy z D5  xy z D6  xyz D7  xyz zyxFig. 4-18 3-to-8-Line Decoder© 2002 Prentice Hall, Inc.M. Morris ManoDIGITAL DESIGN, 3e.D0 D1D2ABED3E10000AX0011BX0101D010111D111011D211101D311110(a) Logic diagram (b) Truth tableFig. 4-19 2-to-4-Line Decoder with Enable Input© 2002 Prentice Hall, Inc.M. Morris ManoDIGITAL DESIGN, 3e.xyzwD0 to D7D8 to D153  8decoderE3  8decoderEFig. 4-20 4  16 Decoder Constructed with Two 3  8 Decoders© 2002 Prentice Hall, Inc.M. Morris ManoDIGITAL DESIGN, 3e.SCxyz012222120345673 ⫻ 8decoderFig. 4-21 Implementation of a Full Adder with a Decoder© 2002 Prentice Hall, Inc.M. Morris ManoDIGITAL DESIGN, 3e.000111100 1D0 D2D3D10 0 11 10111111111111x  D2  D3X000111100 1D0 D2D3D10 0 11 1011111111111111y  D3  D1D2XFig. 4-22 Maps for a Priority Encoder© 2002 Prentice Hall, Inc.M. Morris ManoDIGITAL DESIGN, 3e.D3D2D1D0yxVFig. 4-23 4-Input Priority Encoder© 2002 Prentice Hall, Inc.M. Morris ManoDIGITAL DESIGN, 3e.I0SYI1YI0I1S(a) Logic diagram (b) Block diagramMUX01Fig. 4-24 2-to-1-Line Multiplexer© 2002 Prentice Hall, Inc.M. Morris ManoDIGITAL DESIGN, 3e.Y(a) Logic diagram(b) Function tableI0I1I2I3s1s0s10011s00101YI0I1I2I3Fig. 4-25 4-to-1-Line Multiplexer© 2002 Prentice Hall, Inc.M. Morris ManoDIGITAL DESIGN, 3e.A0Y0Y1Y2Y3A1A2A3B0B1B2B3SE(select)(enable)E100SX01Output Yall 0'sselect Aselect BFunction tableFig. 4-26 Quadruple 2-to-1-Line Multiplexer© 2002 Prentice Hall, Inc.M. Morris ManoDIGITAL DESIGN, 3e.S0S10123yxz01z⬘F(b) Multiplexer implementation(a) Truth table4 ⫻ 1 MUXx00001111y00110011z01010101F01100011F ⫽ zF ⫽ z⬘F ⫽ 0F ⫽ 1Fig. 4-27 Implementing a Boolean Function with a Multiplexer© 2002 Prentice Hall, Inc.M. Morris ManoDIGITAL DESIGN, 3e.S0S1S2012345678 ⫻ 1 MUXCBADF01A0000000011111111B0000111100001111C0011001100110011D0101010101010101F0101100000011111F ⫽ DF ⫽ DF ⫽ D⬘F ⫽ 0F ⫽ 0F ⫽ DF ⫽ 1F ⫽ 1Fig. 4-28 Implementing a 4-Input Function with a Multiplexer© 2002 Prentice Hall, Inc.M. Morris ManoDIGITAL DESIGN, 3e.Normal input A Output Y  A if C  1High–impedance if C  0Control input CFig. 4-29 Graphic Symbol for a Three-State Buffer© 2002 Prentice Hall, Inc.M. Morris ManoDIGITAL DESIGN, 3e.I0I1I2I3S1S0ENSelectEnableYABYSelect(a) 2-to-1- line mux (b) 4 - to - 1 line mux01232 ⫻ 4decoderFig. 4-30 Multiplexers with Three-State Gates© 2002 Prentice Hall, Inc.M. Morris ManoDIGITAL DESIGN, 3e.in outcontrolbufiflin outcontrolbufif0in outcontrolnotiflin outcontrolnotif0Fig. 4-31 Three-State Gates© 2002 Prentice Hall, Inc.M. Morris ManoDIGITAL DESIGN, 3e.ABoutselectFig. 4-32 2-to-1-Line Multiplexer with Three-State Buffers© 2002 Prentice Hall, Inc.M. Morris ManoDIGITAL DESIGN, 3e.Stimulus module Design modulecircuit cr (TA, TB, TC);wire TC;reg TA, TB;module testcircuit module circuit (A, B, C);input A, B;output C;Fig. 4-33 Stimulus and Design Modules Interaction© 2002 Prentice Hall, Inc.M. Morris ManoDIGITAL DESIGN, 3e.ABCDT1T3T4F1F2T2Fig. P4-1© 2002 Prentice Hall, Inc.M. Morris ManoDIGITAL DESIGN, 3e.AFGBCDFig. P4-2© 2002 Prentice Hall, Inc.M. Morris ManoDIGITAL DESIGN, 3e.bcbagdcfe(a) Segment designation (b) Numerical designation for display Fig. P4-9© 2002 Prentice Hall, Inc.M. Morris ManoDIGITAL DESIGN, 3e.B0A0C0C1S0Fig. P4-17 First Stage of a Parallel Adder© 2002 Prentice Hall, Inc.M. Morris ManoDIGITAL DESIGN,