UH COSC 6385 - Memory Hierarchies (II) (17 pages)

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Memory Hierarchies (II)



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Memory Hierarchies (II)

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Pages:
17
School:
University of Houston
Course:
Cosc 6385 - Computer Architecture

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COSC 6385 Computer Architecture Memory Hierarchies II Edgar Gabriel Spring 2010 Edgar Gabriel Cache Performance Avg memory access time Hit time Miss rate x Miss penalty with Hit time time to access a data item which is available in the cache Miss rate ratio of no of memory access leading to a cache miss to the total number of instructions Miss penalty time cycles required for making a data item in the cache COSC 6385 Computer Architecture Edgar Gabriel 1 Processor Performance CPU equation CPU time Clock cycle CPU execution Clock cycles clock cycle time memory stall x Can avg memory access time really be mapped to CPU time Not all memory stall cycles are due to cache misses We ignore that on the following slides Depends on the processor architecture In order vs out of order execution For out of order processors need the visible portion of the miss penalty Memory stall cycles instruction Misses instruction x Total miss latency overlapped miss latency COSC 6385 Computer Architecture Edgar Gabriel Reducing cache miss penalty Five techniques Multilevel caches Critical word first and early restart Giving priority to read misses over writes Merging write buffer Victim caches COSC 6385 Computer Architecture Edgar Gabriel 2 Multilevel caches I Dilemma should the cache be fast or should it be large Compromise multi level caches 1st level small but at the speed of the CPU 2nd level larger but slower Avg memory access time Hit time L1 Miss rate L1 x Miss penalty and Miss penalty L1 Hit time L2 Miss rate L2 x Miss penalty L2 L1 COSC 6385 Computer Architecture Edgar Gabriel Multilevel caches II Local miss rate rate of number of misses in a cache to total number of accesses to the cache Global miss rate ratio of number of misses in a cache number of memory access generated by the CPU 1st level cache global miss rate local miss rate 2nd level cache global miss rate Miss rate L1 x Miss rate L2 Design decision for the 2nd level cache 1 Direct mapped or n way set associative 2 Size of



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