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Penn CIS 240 - CIS 240 HOMEWORK

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Name: 1CSE 240 Autumn 2006Due: Wed. 11 October 2006Intro. to Computer Architecture Homework 4Write your answers on these pages. Additional pages may be attached (with staple) if necessary. Please ensure thatyour answers are legible and show your work. Write your name at the top of each page. Due at the beginning of class.Total points: 621. [6 Points] Instruction Encoding. Suppose a machine encodes instructions in 32 bits according to the followingformat. Also, suppose the encoding must accommodate 110 opcodes and 28 registers.OPCODE SR DR IMM(a) What is the minimum number of bits required to represent the OPCODE field?(b) What is the minimum number of bits required to represent each of the register fields (e.g., DR)?(c) What is the greatest number of bits that are left for the IMM field? If the IMM field encodes a 2’s comple-ment integer, what range of values can be represented with these bits?22. [12 Points] LC-3 Instruction Encoding. For these questions assume the LC-3 instruction encoding (inside theback cover of your textbook). You may also want to consult Appendix A.(a) What is the range of values (in decimal) that may be specified by the immediate field in an AND instruc-tion?(b) What is the range of values (in decimal) that may be specified by the PCoffset field in a BR instruction?(c) What is the range of values (in decimal) that may be specified by the offset field in an LDR instruction?(d) What is the relationship between JMP and RET? In particular, why do they have the same bits in theopcode field?(e) Give the encoding of two LC-3 instructions that together increment register R3 by 20. Complete thefollowing table.Address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Instructionx3001x3002Name: 33. [15 Points] LC-3 Code. Suppose you want to write a program consisting of instructions with the behaviordescribed by the operation in the final column of the following table.Address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Operationx3001 R2 <- M[R1+0]x3002 R3 <- M[R1+1]x3003 R4 <- NOT R3x3004 R4 <- R4 + 1x3005R5 <- R2 + R4x3006 BRzp x3009x3007 M[R1+2] <- R3x3008 BRnzp x3010x3009M[R1+2] <- R2(a) Give the binary encoding of each instruction in the table. Write your answers in the table, above.(b) Trace the execution of the above program, starting at x3001, by completing the following table. Give thePC and operation to execute in the first two columns, and give the state of the registers and condition codesafter the execution of that instruction (leave an entry blank if it is not changed by the instruction). Theinitial state and the effect of the first instruction are given in the first two rows. Assume memory locationsx3100 and x3101 contain 14 and 27, respectively.PC Operation R0 R1 R2 R3 R4 R5 R6 R7 CCs M[x3102]initial state ⇒ 0 x3100 0 3 4 5 6 7 0x3001R2 <- M[R1+0] 14 P(c) In a sentence, what does this code compute?44. [16 Points] LC-3. The following (bit-level) memory contents represent an LC-3 program.Address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Instructionx3001 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 R1 <- M[R0+0]x3002 0 1 0 1 0 1 0 0 1 0 1 0 0 0 0 0x3003 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 1x3004 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 1x3005 0 0 0 1 0 1 1 0 1 1 1 1 1 1 1 1x3006 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1x3007 0 1 1 1 0 1 0 0 0 0 0 0 0 0 1 0(a) First, determine what each instruction does. Write this next to each instruction (above) in a manner similarto that of the previous problem.(b) Next, trace the execution of the above program, starting at x3001, by completing the following table. Givethe PC and instruction to execute in the first two columns, and give the state of the registers and conditioncodes after the execution of that instruction (leave an entry blank if it has not been changed by theinstruction). The initial state and the effect of the first instruction are given in the first two rows. Assumememory locations x3100 and x3101 contain 3 and 2, respectively.PC Instruction R0 R1 R2 R3 R4 R5 R6 R7 CCs M[x3102]initial state ⇒ x3100 1 2 3 4 5 6 7 0x3001 R1 <- M[R0+0] 3 PName: 5(c) Describe what this code does, assuming execution starts at address x3001. What registers or memory serveas input to this code? And what registers or memory serve as output? Be very careful in determining theinput and output (i.e., just because a register appears in the code does not mean that it is input or output).(d) Under what circumstances will this program fail to perform its principal task?65. [12 Points] LC-3 Data-path. Consider the single-cycle LC-3 data-path from lecture.InDataAddress OutDataWEMemory216 by 16 bitPCRd1InData OutData2WERegister FileOutData1Rd2 WrSEXTSEXTZEXTSEXT021021InDataAddress OutDataWEMemory216 by 16 bit101010+1[4:0][5:0][7:0][8:0]++0001616161616161616161616161616Controller33322161616161 2 3 4 5 6 7Rd1Rd2WrGive the control lines for the instructions in the table, below. In each box, place either a constant (e.g., 2), one ormore bits from the instruction (e.g., I[8:6]), or “X” indicating that the value on the control line does not matter.Opcode Registers ControlName I[15:12] I[5] Rd1 Rd2 Wr ¶ · ¸ ¹ º » ¼ADD 0001 0 I[8:6] I[2:0] I[11:9] 1 0 0 0 1 0 1ADD Immed 0001 1LDR 0110 — I[8:6] x I[11:9] 1 2 0 0 0 0 1LD 0010 —STR 0111 —ST 0011 —LEA 1110 —JMP 1100 — I[8:6] x x 0 2∗0 0 1 x 0JSRR 0100 —∗Because the low-order 6 bits of the JMP instruction encoding are all zeros,this control signal causes the mux to select 0.Name: 76. [1 Point] Last and Most Important Question! Give us your feedback.(a) How many hours did you spend on this assignment?(b) On a scale of 1-5, how difficult did you find this assignment? (1-easiest, 5-most difficult)(c) Do you have any other comments on your experience completing this assignment? What are


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