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Self-alignment techniques



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9 5 The Proceedings of the 5th International TFT Conference Self alignment techniques for fabricating a Si H TFTs at 300oC on clear plastic Kunigunde H Cherenack Institute for Electronics Swiss Federal Institute of Technology ETH Z rich Switzerland Bahman Hekmatshoar Sigurd Wagner and James C Sturm Department of Electrical Engineering and Princeton Institute for the Science and Technology of Materials Princeton University Princeton New Jersey USA Abstract We previously demonstrated highly stable backchannel cut and back channel passivated amorphous silicon thin film transistors a Si H TFTs made at 300oC on 2 9 inch x 2 9 inch clear plastic substrates 1 Mechanical stress in the TFT stack causes the substrate to expand or contract which easily results in misalignment between consecutive device layers 2 3 Therefore we developed three selfalignment processes to resolve this issue To process 1 we self aligned the channel passivation in back channel passivated TFTs to the gate To process 2 we self aligned the source drain terminals and the a Si H island layer in backchannel cut TFTs to the gate To process 3 we combined processes 1 and 2 which enabled us to fabricate backchannel passivated TFTs with the channel passivation the source drain terminals and the a Si H layer self aligned to the gate Using these processes we were able to reduce the TFT channel length to 5 m with a 1 m source drain S D overlap and obtained functional devices over the entire surface area of the plastic workpiece 1 Introduction The mechanical stress in a plastic workpiece needs to be designed carefully 1 3 to obtain functional devices on free standing plastic substrates Even if the deposited device layers are crack free the stress in the TFT stack causes the substrate to expand or contract depending on the sign of the strain of the total structure resulting in misalignment between consecutive mask layers Misalignment is defined by 106 x d ppm In this equation d is the local misalignment between the



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