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Self-alignment techniques

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The Proceedings of the 5th International TFT Conference 9.5Self-alignment techniques for fabricating a-Si:H TFTs at 300oC on clear plastic Kunigunde H. Cherenack Institute for Electronics, Swiss Federal Institute of Technology (ETH), Zürich, Switzerland Bahman Hekmatshoar, Sigurd Wagner and James C. Sturm Department of Electrical Engineering and Princeton Institute for the Science and Technology of Materials, Princeton University, Princeton, New Jersey, USA AbstractWe previously demonstrated highly stable back-channel cut and back-channel passivated amorphous silicon thin-film transistors (a-Si:H TFTs) made at 300oC on 2.9-inch x 2.9-inch clear plastic substrates [1]. Mechanical stress in the TFT stack causes the substrate to expand or contract, which easily results in misalignment between consecutive device layers [2,3]. Therefore we developed three self-alignment processes to resolve this issue. To process (1) we self-aligned the channel passivation in back-channel passivated TFTs to the gate. To process (2) we self-aligned the source-drain terminals, and the a-Si:H island layer in back-channel cut TFTs to the gate. To process (3) we combined processes (1) and (2), which enabled us to fabricate back-channel passivated TFTs with the channel passivation, the source-drain terminals and the a-Si:H layer self-aligned to the gate. Using these processes we were able to reduce the TFT channel length to 5μm with a 1 μm source/drain (S/D) overlap, and obtained functional devices over the entire surface area of the plastic workpiece. 1. Introduction The mechanical stress in a plastic workpiece needs to be designed carefully [1-3] to obtain functional devices on free-standing plastic substrates. Even if the deposited device layers are crack-free, the stress in the TFT stack causes the substrate to expand or contract (depending on the sign of the strain of the total structure), resulting in misalignment between consecutive mask layers. Misalignment is defined by  { 106 x d/ [ppm]. In this equation d is the local misalignment between the alignment mark in the bottom layer (patterned before device layer deposition) and the alignment mark in the top layer (patterned after device layer deposition).  is the distance from the center of the substrate to the center of the alignment mark where the misalignment is calculated. In the work that we present here we developed three self-alignment processes for TFT fabrication on clear plastic. We refer to them as SA-1, SA-2 and SA-3 for easy reference. For SA-1 we use a back-channel passivated TFT process to self-align the gate (mask 1) and the channel passivation (mask 2). This approach is similar to that published by Cheng [4]. For SA-2 we use a back-channel cut TFT process to align the gate (mask 1) to the S/D terminals (mask 2) and the a-Si:H islands (mask 3); finally SA-3 is a combination of SA-1 and SA-2. The numbers indicated in the definitions of SA-1, SA-2 and SA-3 are the numbers of the masks that would be used to pattern these layers if we were using standard photolithography. The distinguishing feature common to all of these self-alignment methods is that they rely on a previously patterned device layer as a mask to pattern a subsequent device layer. This is in contrast to a standard photolithographic process where patterns are transferred from a rigid glass mask to the top device layer on the substrate. Device layers (such as metal layers) that block UV light act as ‘masks’ in self-alignment processes. In our process we always align all mask layers at the center of the substrate, and measure misalignment at the edge. Figure 1 shows a schematic of a substrate after patterning the second mask layer using photolithography, indicating where d and are measured. For TFTs this misalignment has the following implication: if the device layers delineating the TFT channel do not overlap the TFT will not turn on. Figure 1 Schematic indicating where d and are measured to calculate the degree of misalignment between mask layers (not to scale) Bottom alignment mark Top alignment mark Center of substrate (top and bottom alignment marks overlap) d Figure 3 Schematic cross section indicating the critical overlaps (1) and (2) for bottom-gate back-channel passivated a-Si:H TFTs (1) (2) (a) (b) Figure 2 a-Si:H TFT structures: (a) back-channel cut, bottom-gate staggered source-drain, (b) back-channel passivatedCr/Al/Crn+ nc-Si a-Si SiNx clear plastic n+nc-SiSiNx channel passivationThe Proceedings of the 5th International TFT Conference 9.5 A schematic showing the back-channel cut and back-channel passivated TFT structures that we fabricated in our work is shown in Figure 2. The position of the critical alignment gaps/overlaps between (1) the gate and the channel passivation and (2) between the gate and the S/D terminals for a back-channel passivated TFT are shown in Figure 3. Another issue to be considered is the impact of misalignment on the minimum TFT channel dimensions that can be designed in a mask set for device fabrication on plastic. To counteract misalignment it is customary to fabricate TFTs with large S/D overlaps with the gate (10μm), and that have relatively long channels (our usual TFT channel length is 40μm). A reduction in the misalignment between device layers will allow us to reduce the TFT channel dimensions. 2. Device Fabrication 2.1 Substrate Preparation Our 75- m-thick optically clear-plastic substrates are cut into 7.4 × 7.4 cm2 workpieces. These substrates have a working temperature  3000C. Their in-plane coefficient of thermal expansion SUBSTRATE is  10 ppm/C, which is sufficiently low to obtain intact device layers in a 3000C process [1]. We prepare our clear plastic substrate as described in [1]. Following the plasma treatments the front and back of the substrate are coated with a SiNx barrier layer. In each case, the barrier layer deposition was preceded by the deposition of 30nm of SiNx at 213mW/cm2 (ultra-high power) and 2800C to promote adhesion. The 200nm thick front barrier layer was deposited at a power density of 18mW/cm2 at 2800C and the 300nm thick back barrier layer was deposited at a power density of 18mW/cm2 at 2800C. 2.2 TFT Device Structure The SiNx gate dielectric is 300nm thick. We chose an a-Si:H thickness of 25nm to make the layers sufficiently transparent for self-alignment [4]. The n+ doped layer is 50nm


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