Analog Dialogue 33-8 (1999) 1Analog-to-DigitalConverter Architec-tures and Choices forSystem DesignBy Brian BlackHow important are the differences between sigma-delta andsuccessive-approximation architectures in choosing an analog-to-digital (A/D) converter? They can often be an important factor ininitiating the selection of a converter for a specific application. Wedescribe here four major circuit architectures used in A/D converter(ADC) design and outline the role they play in converter choicefor various kinds of applications. The descriptions are augmentedby three examples that illustrate tradeoffs and issues associatedwith architectural considerations.Though not detailed or exhaustive, this overview is intendedto raise issues that should be understood when consideringconverters of different architectures. Sources of more-detailedinformation on converter architectures can be found in theReferences and at Internet sites indicated at appropriate points.As one might expect in a survey of this kind, these descriptionsare not comprehensive; and variations within each of thearchitecture families make generalizations less than fully accurate.Nevertheless, such generalizations are useful for the systemdesigner to keep in mind when conducting a high level overviewof a proposed system’s requirements.CONVERTER ARCHITECTURESAn overwhelming variety of ADCs exist on the market today, withdiffering resolutions, bandwidths, accuracies, architectures,packaging, power requirements, and temperature ranges, as wellas hosts of specifications, covering a broad range of performanceneeds. And indeed, there exists a variety of applications in data-acquisition, communications, instrumentation, and interfacing forsignal processing, all having a host of differing requirements.Considering architectures, for some applications just about anyarchitecture could work well; for others, there is a “best choice.”In some cases the choice is simple because there is a clear-cutadvantage to using one architecture over another. For example,pipelined converters are most popular for applications requiring athroughput rate of more than 5 MSPS with good resolution. Sigma-delta converters are usually the best choice when very highresolution (20 bits or more) is needed. But in some cases the choiceis more subtle. For example, the sigma-delta AD7722 and thesuccessive-approximations AD974 have similar resolution (16 bits)and throughput performance (200 kSPS). Yet the differences intheir underlying architectures make one or the other a betterchoice, depending on the application.The most popular ADC architectures available today are successiveapproximations (sometimes called SAR because a successive-approximations (shift) register is the key defining element), flash(all decisions made simultaneously), pipelined (with multiple flashstages), and sigma-delta (Σ∆), a charge-balancing type. All A/Dconverters require one or more steps involving comparison of aninput signal with a reference. Figure 1 shows qualitatively howflash, pipelined, and SAR architectures differ with respect to thenumber of comparators used vs. the number of comparison cyclesneeded to perform a conversion.1101001,00010,000FLASHC = 2n –1t = 1PIPELINEC P ⴛ 2n/Pt = PFLASH16 BIT12105BIT812 BIT16 BITSARC = 1t nSUCCESSIVEAPPROXIMATION1 BIT1 5 10 15DECISION CYCLES – tNUMBER OF COMPARATORS – C810161210Figure 1. Tradeoff between decision cycles and comparators.FLASH CONVERTERSConceptually, the flash architecture (illustrated in Figure 2) is quitestraightforward: a set of 2n–1 comparators is used to directlymeasure an analog signal to a resolution of n bits. For a 4-bit flashADC, the analog input is fed into 15 comparators , each of whichis biased to compare the input to a discrete transition value. Thesevalues are spaced one least-significant bit (LSB = FS/2n) apart.The comparator outputs simultaneously present 2n–1 discretedigital output states. If for example the input is just above 1/4 offull scale, all comparators biased to less than 1/4 full scale willoutput a digital “1,” and the others will output a digital “0.”Together, these outputs can be read much like a liquidthermometer. The final step is to level-decode the result intobinary form.2n – 1(FULL SCALE)...AINLEVELDECODEDIGITAL2n2n – 2(FULL SCALE)2n2(FULL SCALE)2n1(FULL SCALE)2nFigure 2. Basic flash architecture.Design Considerations and Implications: The flash architecture hasthe advantage of being very fast, because the conversion occurs ina single ADC cycle. The disadvantage of this approach is that itrequires a large number of comparators that are carefully matchedand properly biased to ensure that the results are linear. Since thenumber of comparators needed for an n-bit resolution ADC isequal to 2n–1, limits of physical integration and input loading keepthe maximum resolution fairly low. For example, a 4-bit ADCrequires 15 comparators, an 8-bit ADC requires 255 comparators,and a 16-bit ADC would require 65,535 comparators! Formore about flash ADCs, see http://www.analog.com/supportstandard_linear/seminar_material/practical_design_techniques/Section4.pdf.2 Analog Dialogue 33-8 (1999)PIPELINED ARCHITECTUREThe pipelined (or pipelined-flash) architecture effectively overcomesthe limitations of the flash architecture. A pipelined converterdivides the conversion task into several consecutive stages. Eachof these stages, as shown in Figure 3, consists of a sample-and-hold circuit, an m-bit ADC (e.g., a flash converter), and an m-bitD/A converter (DAC). First the sample and hold circuit of thefirst stage acquires the signal. The m-bit flash converter thenconverts the sampled signal to digital data. The conversion resultforms the most significant bits of the digital output. This samedigital output is fed into an m-bit digital-to-analog converter, andits output is subtracted from the original sampled signal. Theresidual analog signal is then amplified and sent on to the nextstage in the pipeline to be sampled and converted as it was in thefirst stage. This process is repeated through as many stages as arenecessary to achieve the desired resolution. In principle, a pipelinedconverter with p pipeline stages, each with an m-bit flash converter,can produce a high-speed ADC with a resolution of n = p × m bitsusing p × (2m–1) comparators. For example, a 2-stage pipelinedconverter with 8-bit resolution requires 30 comparators, and a 4-stage 16-bit ADC requires only 60