Name Manoj Geo Varghese06 November 2000Name Manoj Geo VargheseFall 2000ECE 734 Project Proposal MMX Technology Optimization : A Study To write optimized MMX code, we must - Understand the MMX instruction latencies- Know how to pair MMX instructions- Learn how to efficiently mix MMX & regular integer instructions- Take cache structure into consideration.- Software PipeliningThe project shall consider a super scalar machine and try to discuss all aforesaid points with reference to it.A Brief Preview to the 1. Latency Rules for e.g. modification of MMX register value, multiplication, and memory and register interaction etc. Discussion with reference to super scalar architecture for e.g. in Pentium viz. U and V pipes.2. The pairing of MMX instructions also plays an important/major role in optimizing MMX Code. Certain pair of instructions can be executed simultaneously in the U and V pipes and still avoids stalling. The project shall present a case study in this topic with focus on actual MMX instructions and applications.3. Efficient mix of MMX instructions and regular integer instructions. Stress on use of MMX instructions at a block level and avoid using them at the instruction level and reasons for it. Examples will be discussed for this part.4. Cache memory is of concern in optimization. How to optimize the use of primary cache and alsoreference to the secondary cache. A small case study will be presented on this portion of the work.5. Finally this project will discuss pipelining feature with reference to Multimedia Application. This project will present a case work on this topic.References( Books, URLs, Papers):[1] David Bistry, C. Dulong, M. Gutman, M. Julier and M. Keith, Intel- Corp. The Complete Guide to MMXTM Technology-Vol II, McGraw Hill Inc., 1997[2] Hennesey, John L . and David A Paterrson, Computer Architecture : A Quantitative Approach. 2nd Edition Morgan Kaufmann,1996[3] Yen-Kuang Chen ,“Digital Signal Processing on MMXTM Technology”,Microprocessor Research Labs, Intel- Corporation.[4] S.Thakkar and T.Huff,” Internet Streaming SIMD Extensions”, IEEE Computer vol. 32[6] A. Peleg U.Weiser, “ The MMX Technology Extension to Intel Architecture,” IEEE Micro,vol. 16, no.4, pp. 42-50,Aug. 1996[7] R. B. Lee “Accelerating Multimedia With Enhanced Processors”, IEEE Micro, vol 15, no 2, Apr. 1995[8] http://www.intel.com/home/pentium4/tech-info.htm[9] http://www.pctechguide.com [10]http://www.bdti.com/procsum/index.htm06 November
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