14:332:331 Computer Architecture and Assembly Language Spring 06 Week 2 : ISA, MIPS AssemblyReview I: Execute CycleReview II: word lengthAssembly LanguageMIPS R3000 Instruction Set ArchitectureMIPS Arithmetic InstructionCompiling More Complex StatementsRegistersMIPS Register FileNaming Conventions for RegistersRegisters vs. MemoryAccessing MemoryProcessor – Memory InterconnectionsMIPS Data TypesByte AddressesAddressing Objects: Endianess and AlignmentMIPS Memory AddressingCompiling with Loads and StoresCompiling with a Variable Array IndexMIPS Instructions, so farMachine Language - Arithmetic InstructionMIPS Instruction FieldsMachine Language - Load InstructionMemory Address LocationMachine Language - Store InstructionAssembling CodeReview: MIPS Data TypesBeyond NumbersLoading and Storing BytesExample of Loading and Storing BytesReview: MIPS Instructions, so farReview: MIPS R3000 ISA331 W02.1 Spring 0614:332:331Computer Architecture and Assembly LanguageSpring 06Week 2 : ISA, MIPS Assembly[Adapted from Dave Patterson’s UCB CS152 slides andMary Jane Irwin’s PSU CSE331 slides]331 W02.2 Spring 06Review I: Execute CycleQ1: How does control know which instruction to fetch?Q2: who does decode? What happens in decode phase?Q3: How do control and datapath interact to finish exec phase?Q4: What does datapath have? FetchDecodeExec331 W02.3 Spring 06Review II: word lengthWhat does 32-bit architecture mean?331 W02.4 Spring 06Assembly Language Language of the machineMore primitive than higher level languagese.g., no sophisticated control flowVery restrictivee.g., MIPS arithmetic instructionsWe’ll be working with the MIPS instruction set architecturesimilar to other architectures developed since the 1980'sused by NEC, Nintendo, Silicon Graphics, Sony, …32-bit architecture -32 bit data line and address line-data and addresses are 32-bit331 W02.5 Spring 06MIPS R3000 Instruction Set ArchitectureInstruction CategoriesLoad/StoreComputationalJump and BranchFloating Point-coprocessorMemory ManagementSpecialR0 - R31PCHILOOPOPOPrsrtrd sa functrsrtimmediatejump target 3 Instruction Formats: all 32 bits wideRegistersQ: How many already familiar with MIPS ISA?331 W02.6 Spring 06MIPS Arithmetic InstructionMIPS assembly language arithmetic statementadd $t0, $s1, $s2sub $t0, $s1, $s2Each arithmetic instruction performs only one operationEach arithmetic instruction specifies exactly three operandsdestination  source1 op source2Those operands are contained in the datapath’s register file ($t0, $s1,$s2)Operand order is fixed (destination first)331 W02.7 Spring 06Compiling More Complex StatementsAssuming variable b is stored in register $s1, c is stored in $s2, d is stored in $s3 and the result is to be left in $s0, and $t0 is a temporary register, what is the assembler equivalent to the C statementh = (b - c) + d331 W02.8 Spring 06RegistersRegisters areFaster than main memoryCan hold variables so that-code density improves (since registers are named with fewer bits than a memory location) – why is that?Register addresses are indicated by using $331 W02.9 Spring 06MIPS Register FileOperands of arithmetic instructions must be from a limited number of special locations contained in the datapath’s register fileHolds thirty-two 32-bit registers-With two read ports and-One write portRegister Filesrc1 addrsrc2 addrdst addrwrite data32 bitssrc1datasrc2data32locations325325532331 W02.10 Spring 060 $zero constant 01 $at reserved for assembler2 $v0 expression evaluation &3 $v1 function results4 $a0 arguments5 $a16 $a27 $a38 $t0 temporary: caller saves. . . (callee can clobber)15 $t7Naming Conventions for Registers16 $s0 callee saves. . . (caller can clobber)23 $s724 $t8 temporary (cont’d)25 $t926 $k0 reserved for OS kernel27 $k128 $gp pointer to global area29 $sp stack pointer30 $fp frame pointer31 $ra return address331 W02.11 Spring 06Registers vs. MemoryArithmetic instructions operands must be registers, — only thirty-two registers providedWhat about programs with lots of variables?Store variables in the memoryLoad variables from memory to registers before use; store them back to memory after use. ProcessorControlDatapathMemoryDevicesInputOutput331 W02.12 Spring 06MIPS has two basic data transfer instructions for accessing memorylw $t0, 4($s3) #load word from memorysw $t0, 8($s3) #store word to memoryThe data transfer instruction must specifywhere in memory to read from (load) or write to (store) – memory addresswhere in the register file to write to (load) or read from (store) – register destination (source)The memory address is formed by summing the constant portion of the instruction and the contents of the second registerAccessing Memory331 W02.13 Spring 06Memory is viewed as a large, single-dimension array, with an addressA memory address is an index into the arrayProcessor – Memory InterconnectionsProcessorMemoryAddressablelocationsread addr/write addrread datawrite data232 Q: what should be the smallest addressable unit?331 W02.14 Spring 06MIPS Data TypesInteger: (signed or unsigned) 32 bitsCharacter: 8 bitsFloating point numbers: 32 bitsMemory addresses (pointers): 32 bitsInstructions: 32 bitsBit String: sequence of bits of a particular length 8 bits is a byte 16 bits is a half-word 32 bits (4 bytes) is a word 64 bits is a double-word331 W02.15 Spring 06Byte AddressesSince 8-bit bytes are so useful, most architectures address individual bytes in memory memory: 232 bytes = 230 wordsTherefore, the memory address of a word must be a multiple of 4 (alignment restriction)Alignment restriction: requires that objects fall on address that is multiple of their size.0 1 2 3AlignedNotAligned331 W02.16 Spring 06Addressing Objects: Endianess and AlignmentBig Endian: leftmost byte is word address IBM 360/370, Motorola 68k, MIPS, Sparc, HP PALittle Endian: rightmost byte is word addressIntel 80x86, DEC Vax, DEC Alpha (Windows NT)msb lsb3 2 1 0little endian byte 00 1 2 3big endian byte 0331 W02.17 Spring 06MIPS Memory AddressingThe memory address is formed by summing the constant portion of the instruction and the contents of the second (base) registerlw $t0, 4($s3) #what? is loaded into $t0 sw $t0, 8($s3) #$t0 is stored